Timing based scan chain implementation in an IC design

Details Timing based scan chain implementation in an IC design Timing based scan chain implementation in an IC design

2006-10-24

2006-10-24

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07127695

ABSTRACT:
For use with a design database and a timing database, a computer implemented process for electronic design automation comprising: receiving a netlist that includes cells interconnected by circuit paths, wherein a plurality of the cells are scan cells connected in at least one scan chain; ordering the scan cells according to a prescribed scan cell ordering rule so as to produce a plurality of ordering relationships among scan cells; assigning respective weights from a first category of one or more weights to respective prescribed scan cell order relationships among scan cells of the netlist; assigning respective weights from a second category of one or more weights to prescribed circuit path relationships among cells of the netlist; and determining a physical placement of the cells of the netlist, including the scan cells, using a cost function that places the cells according to the assigned weights.

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