Burst mode implementation in a memory device

Details Burst mode implementation in a memory device Burst mode implementation in a memory device

2006-09-19

2006-09-19

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S104000, C365S222000, C365S230010

Reexamination Certificate

active

07111143

ABSTRACT:
A memory device, such as a DRAM, includes a memory array that is accessible for writing data in and reading data out, and a command decoder that decodes input control signals to produce commands for accessing the memory array. The set of commands for controlling access to the memory device can include a first memory access command for accessing the memory array using a first burst length, a second memory access command for accessing the memory array using a second burst length, and a terminate command that terminates a current memory access. The memory device can include a mode register that stores memory access parameters associated with accessing the memory array, including the burst lengths. Access to the memory array is switchable between the first burst length and the second burst length without altering the memory access parameters in the mode register.

REFERENCES:
patent: 5307320 (1994-04-01), Farrer et al.
patent: 5566119 (1996-10-01), Matano
patent: 6088760 (2000-07-01), Walker et al.

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