Burst length detection circuit for detecting a burst end time po

Details Burst length detection circuit for detecting a burst end time po Burst length detection circuit for detecting a burst end time po

1996-06-28

1998-09-08

Lee, Thomas C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711219, G06F 1328

Patent

active

058059288

ABSTRACT:
A burst length detection circuit comprising at least two registers, each the registers storing a corresponding one of at least two external address signals therein, at least two internal address signal generators, each of the internal address signal generators inputting a corresponding one of the at least two external address signals as its initial value and sequentially incrementing it by one in response to a clock signal to sequentially generate internal address signals, at least two comparators, each of the comparators being operated in response to a control signal to compare an output signal from a corresponding one of the at least two internal address signal generators with an output signal from a corresponding one of the at least two registers, a logic circuit for performing a logic operation with respect to output signals from at least two comparators to detect a burst end time point, and a burst signal generation circuit for generating a burst mode signal with a desired logic value in response to an external burst command signal and a burst end signal from the logic circuit.

REFERENCES:
patent: 5268865 (1993-12-01), Takasugi
patent: 5319759 (1994-06-01), Chan
patent: 5345573 (1994-09-01), Bowden et al.
patent: 5452261 (1995-09-01), Chung et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5675549 (1997-10-01), Ong et al.

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