Burst EDO memory device having pipelined output buffer

Details Burst EDO memory device having pipelined output buffer Burst EDO memory device having pipelined output buffer

1995-02-10

1997-07-29

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, G11C 700

Patent

active

056527241

ABSTRACT:
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. A two stage pipelined output buffer latches read data in a first stage while data from a second stage is driven from the device. Internal read lines may become invalid in preparation for additional access cycles after the data is latched in the first stage. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

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Mosel-Vitelic V53C8257H DRAM Specification Sheet, 20 pgs.

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