Burn-in test circuit for semiconductor memory device

Details Burn-in test circuit for semiconductor memory device Burn-in test circuit for semiconductor memory device

1993-09-23

1995-09-19

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

36518909, 365193, G11C 2900

Patent

active

054522536

ABSTRACT:
For enabling burn-in test in a memory device such that a test mode timing signal and detected voltage level of an external power supply are combined in order to maintain compatibility with conventional timing signals, and for preventing the burn-in test circuit from dissipating power in a standby state, there is provided a sense control circuit for producing a short duration enable pulse in response to an input level of timing signals such as WCBR, CBR, or ROR, and a voltage sensor for sensing the input voltage level of the external power supply voltage during the short duration pulse. Also, the circuit includes a burn-in sensor which generates a signal output which determines set or reset of the burn-in test mode in response to the timing signals and the detected level of the voltage sensor. Since the voltage sensor is operated only when the short duration pulse is applied, the power consumption in the voltage sensor is negligible even during the sensing operation of the external supply voltage. Further, the burn-in test mode is activated in the memory device if the external input signals satisfy the particular condition and the level of the external supply voltage is higher than the preset burn-in test voltage, thereby the memory device is prevented from entering into the burn-in test mode due to noise of the external power supply voltage.

REFERENCES:
patent: 5063304 (1991-11-01), Iyengar
patent: 5111433 (1992-05-01), Miyamoto
patent: 5119337 (1992-06-01), Shimizu et al.

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