Burn-in test circuit and method in semiconductor memory device

Details Burn-in test circuit and method in semiconductor memory device Burn-in test circuit and method in semiconductor memory device

1995-12-13

1997-06-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36523006, G11C 700

Patent

active

056383312

ABSTRACT:
Disclosed is a burn-in test circuit and method of a semiconductor memory device which is capable of applying a stress voltage simultaneously to a plurality of word lines and which is operative when the device is in either a wafer or package state. The disclosed burn-in test circuit and method includes the capability of fusably disabling burn-in test operations in the memory device once the burn-in test is completed. The burn-in test circuit includes a burn-in enable signal generator for receiving a predetermined timing of external signals by which the burn-in test is selected, and for generating a burn-in enable signal in response. A row address decoder, responsive to the burn-in enable signal, places the word lines of the device in a high-impedance state so that a word line stress input unit can simultaneously apply a stress voltage to the word lines to perform the burn-in test. Upon completion of the burn-in test, the burn-in enable signal generator fusably disables the burn-in enable signal. The burn-in test method includes writing background data to each of the memory cells, enabling a burn-in test according to a predetermined timing of external signals, placing memory word lines in a high-impedance state, applying a stress voltage to the word lines, and then fusably disabling the subsequent performance of the burn-in test.

REFERENCES:
patent: 5381373 (1995-01-01), Ohsawa
patent: 5452253 (1995-09-01), Choi

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