Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-05-02
1999-03-09
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Testing
365191, G11C 700
Patent
active
058810048
ABSTRACT:
A burn-in stress control circuit for an integrated memory device, such as DRAM, includes a first logic gate for receiving a burn-in enable signal and outputting an inverted burn-in enable signal, a resistor having a first terminal connected to the input terminal of the first logic gate, a first capacitor connected between the second terminal of the resistor and ground. A first transistor having a control terminal connected to the second terminal of the resistor and a first main terminal connected to a source voltage, is activated only when the burn-in enable signal is a high logic signal, thereby outputting the source voltage to a second main terminal of the first transistor. A second transistor having a control terminal connected to an output terminal of the first logic gate, a first main terminal connected to ground and a second main terminal connected to the second main terminal of the first transistor, is activated only when the burn-in enable signal is a low logic signal. Thus, peak current applied to a memory cell array, and noise can be reduced.
REFERENCES:
patent: 5590079 (1996-12-01), Lee
patent: 5790465 (1998-08-01), Roh
Samsung Electronics Co,. Ltd.
Zarabian A.
LandOfFree
Burn-in stress control circuit for a semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Burn-in stress control circuit for a semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Burn-in stress control circuit for a semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1328077