Burn-in circuit and method therefor of semiconductor memory devi

Details Burn-in circuit and method therefor of semiconductor memory devi Burn-in circuit and method therefor of semiconductor memory devi

1994-11-28

1995-11-28

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 700

Patent

active

054714290

ABSTRACT:
The present invention pertains to semiconductor memory devices and more particularly to a burn-in circuit of such devices and burn-in method which improve reliability of a static random access memory RAM. The semiconductor memory device according to the present invention, which includes a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, and a column decoder for selecting the column of the memory cell array, comprises an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, and a burn-in control circuit for inputting the output signal of the read/write control circuit, supplying a burn-in signal responsive to the data input through the input/output line control circuit to the row decoder and column decoder, and enabling a burn-in test of the same chip after a package process.

REFERENCES:
patent: 4380805 (1983-04-01), Proebsting
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5282167 (1994-01-01), Tanaka et al.
patent: 5293340 (1994-03-01), Fujita
patent: 5353254 (1994-10-01), Sakamoto
patent: 5371710 (1994-12-01), Ogihara
patent: 5373472 (1994-12-01), Ohsawa

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