Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-03
2004-03-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S234000, C438S246000, C257S301000
Reexamination Certificate
active
06703274
ABSTRACT:
TECHNICAL FIELD
The field of the invention is that of forming DRAM cells employing vertical transistors in a trench capacitor.
BACKGROUND OF THE INVENTION
As the minimum feature size is reduced in back to back vertical MOSFET DRAM cells, the P-well doping required to avoid interaction between cells must be increased. If not, two cells that share a bitline could affect one another. However, increased P-well doping in the vicinity of the buried strap diffusion is known to result in an increased electric field, storage node junction leakage and reduction of the retention time, so that reduced P-well doping is preferred for better performance of the cell. There is a conflict between reduced interaction between cells and maintaining retention time within a cell. This conflict means that the problem cannot be solved by changing the dopant concentration in the P-well. In particular, simply increasing the P-well concentration increases the leakage current from the cell, which causes the charge stored in the cell to leak out at a greater rate. The increased leakage means, in turn, that the refresh rate of reading data out of the cell and writing the same data back in (with the standard new value for the voltage stored in the capacitor) must be increased so that the system can read the data out before it has degraded so much that the state of the data cannot be determined.
An approach used to limit cell to cell interaction is the reduction of the spatial extent of the buried strap diffusion, since the edge of the diffusion will mark the start of the depletion, and/or reducing the abruptness of the doping profile. This approach has not been very successful because high temperature processes following buried strap formation spread the outdiffusion.
In the past, arsenic, which forms an abrupt concentration profile, has been used as the dopant in the buried strap, since it produces a small diffused region. Phosphorous has not been used, though it would produce a smoother dopant profile, because it spreads over a much greater extent that arsenic. Smoothing out the edge or tail of the buried strap diffusion is another approach to limit the interactions from one cell to another. The use of phosphorous would indeed produce increased smoothness, but at the cost of spreading the geometrical extent of the diffusion, and thus spreading the effect of one cell on another cell.
A related problem to the extent of the buried strap is the thickness of the trench top oxide insulator between the top of the capacitor electrode and the transistor gate. If the Trench top oxide is too thin, there can be leakage or even a short. If it is too thick, so that there is no adequate overlap between the strap outdiffusion and the gate conductor, the current drive of the transistor can be degraded.
SUMMARY OF THE INVENTION
The invention relates to a method of forming a DRAM cell employing a vertical transistor in a trench capacitor, with reduced outdiffusion of the buried strap.
Accordingly, a method is provided of forming a DRAM cell. The method includes forming a trench in a semiconductor substrate and forming a capacitor in a lower portion of the trench having an insulating trench collar and a capacitor center electrode. The center electrode is recessed to a capacitor depth, leaving an electrode top surface. The collar is then recessed below the electrode top surface, thereby forming a buried strap aperture between the center electrode and the trench sidewalls. The buried strap aperture is filled with a temporary insulator. A set of isolation trenches are formed in the substrate to an isolation trench depth and then filled with an insulator. After forming and filling the isolation trenches, a conductive buried strap is formed in contact with the center electrode and adjacent to the trench sidewalls. A separation insulator is then formed above the buried strap, and a gate insulator is formed adjacent the trench sidewalls and above the buried strap. Thereafter, a transistor gate electrode is then deposited above the separation insulator.
According to an aspect of the invention, high temperature processes are performed before the buried strap is formed, thereby reducing the extent of outdiffusion of the buried strap.
According to another aspect of the invention, isolation trenches for isolating neighboring DRAM cell and/or neighboring transistors are formed before the buried strap is formed.
According to another aspect of the invention, a strap diffusion is formed which is self-aligned to the vertical gate conductor.
As may be possible according to an aspect of the invention is the avoidance of any pad oxide undercut.
REFERENCES:
patent: 6399977 (2002-06-01), Alsmeier
patent: 2002/0094619 (2002-07-01), Mandelman et al.
patent: 2002/0197792 (2002-12-01), Hsu et al.
Chidambarrao Dureseti
Divakaruni Ramachandra
Mandelman Jack A.
Van Roijen Raymond
Elms Richard
Smith Brad
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