Buried interconnect structure for semiconductor devices

Details Buried interconnect structure for semiconductor devices Buried interconnect structure for semiconductor devices

1991-12-17

1994-07-26

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257333, 257389, 257632, 257748, 257750, 257754, 257755, 257757, 257 49, 257 66, 257763, 257 52, H01L 2702, H01L 2348, H01L 2946, H01L 2962

Patent

active

053329139

ABSTRACT:
An improved density semiconductor device having a novel buried interconnect is described. The buried interconnect electrically connects electrical device regions on a semiconductor substrate such that other structures may directly overlie the buried interconnect but not be electrically connected to the electrically conductive portions of the interconnect. The interconnect is composed of a buried conductor and conductive segments. The conductive segments are electrically joined to the buried conductor so as to form an electrical pathway. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. A nonconductive portion of selective poly-epi silicon is then formed over the buried conductor by oxidizing at least some of the selective poly-epi silicon layer. This nonconductive portion of the selective poly-epi silicon allows other structures to be formed over the buried conductor which are not in direct electrical contact with the buried interconnect. These other structures include elevated source/drain type structures, gates and silicidized or refractory metal local interconnects. These other structures may be selectively connected electrically to the conductive portions of the buried interconnect by the use of silicide segments or by the use of silicide segments connected electrically to titanium nitride pads. The conductive portion of the buried interconnect includes the buried conductor, and conductive segments which are formed by either silicon or silicide and which may include refractory metal pads. Silicide segments and titanium nitride pads are formed by depositing, annealing and etching a layer of refractory metal.

REFERENCES:
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D. C. Chen, et al., A New Device Interconnect Scheme For Sub-micron VLSI, IEDM, pp. 118-121, (1984).
V. V. Lee, et al., A Selective CVD Tungsten Local Interconnect Technology, IEDM, pp. 450-453, (1988).
T. E. Tang, et al., Titanium Nitride Local Interconnect Technology for VLSI, IEEE Transactions on Electron Devices, col. ED-34, No. 3, pp. 682-687, (Mar. 1987).
D. C. Thomas, et al., A Multileve Tungsten Interconnect Technology, IEDM, pp. 466-469, (1988).
R. A. Chapman, et al., An 0.8 .mu.m CMOS Technology For High Performance Logic Applications, IEDM, pp. 362-365, (1987).
F. Mieno, et al., Novel Selective Poly-And Epitaxial-Silicon Growth (SPEG) Technique For ULSI Processing, IEDM, pp. 16-19, (1987).

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