Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-09
2001-05-15
Pham, Long (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S223000, C438S224000, C438S424000, C438S232000
Reexamination Certificate
active
06232165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a structure to absorb minority charge carriers within an MOS transistor and, more particularly, to buried guard rings to prevent latch-up in a complementary metal-oxide semiconductor (“CMOS”) integrated circuit.
2. Description of the Related Art
A CMOS integrated circuit device, by definition, includes at least one p-channel and one n-channel metal-oxide semiconductor field-effect transistor (“MOSFET”). The formation of the MOSFETs leads to the formation of parasitic bipolar junction transistors (“BJTs”). During normal device operations, parasitic transistors are not turned-on and therefore do not affect device operations. However, under certain transient conditions, such as voltage surges, parasitic BJTs may be turned-on and the device is said to be “latched-up.”
A parasitic BJT may be turned-on by migrating charge carriers, such as holes to the base, or the n-well region, of a pnp BJT and electrons to the base, or the p-well region, of an npn BJT. Charge carriers can also migrate from the substrate beneath the active regions of the CMOS circuit. In addition, because the collector of a pnp BJT is connected to the base of an npn BJT and the collector of the npn BJT is connected to the base of the pnp BJT, when one parasitic BJT is turned-on by the migrating charge carriers, the other BJT will also be turned on. In addition, if one npn-pnp BJT pair is turned-on, other parasitic BJT pairs in the device will likewise be turned-on, thereby creating a feedback loop within the device. Such a feedback loop consumes power, reduces device speed, and sometimes renders the device inoperative. Once formed, the feedback loop cannot be severed easily. The probability of latch-up increases as device size becomes smaller because undesired charge carriers that create the latch-up triggering current have a greater chance of reaching the areas of the device to trigger latch-up.
Latch-ups may be prevented by stopping the migration of charge carriers or substantially reducing the number of migrating charge carriers. Two known methods have been employed to prevent latch-ups. One method employs “guard rings,” or heavily doped p-type material in a p-well and heavily doped n-type material in an n-well that act as “sinks” to divert the undesired minority charge carriers away from the parasitic BJTs. Guard rings are inserted from the surface to form vertical barriers to charge carrier flow and prevent latch-up by reducing the number of electrons and holes that reach critical parts of the CMOS device to trigger latch-up.
The other method places insulating materials in the shallow surface between active regions of the device to act as barriers to carrier charge flow. These insulating barriers are known as shallow trench isolation (“STI”) structures.
Because the depth of guard rings and STIs is limited by the fabrication process, charge carriers may still migrate underneath them. Therefore, neither method, by itself or in combination, effectively prevents the flow of carriers to or from the substrate. This charge carrier flow is also known as leakage current.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to buried guard rings that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawing.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a CMOS integrated circuit device that includes a first well region of a first conductivity type in the device substrate and a second well region contiguous with the first well region. The first well region includes first and second spaced-apart regions of a second conductivity type, a channel region between the first and second spaced-apart regions, a trench isolation structure contiguous with the first spaced-apart region, and a doped diffused region. The doped diffused region extends at least between a region underneath the trench isolation structure and a region underneath the first spaced-apart region. The doped diffused region is a first conductivity type.
In another aspect, the doped diffused region is connected to ground.
In yet another aspect, the doped diffused region is connected to a voltage source.
Also in accordance with the invention, there is provided a twin-well CMOS integrated circuit device that includes a semiconductor substrate, a p-well region in the substrate and an n-well region in the substrate. The p-well region includes first and second spaced-apart n-type regions, a channel region between the first and second spaced-apart regions, a first trench isolation structure contiguous with the first spaced-apart region, and a p-type doped diffused region that extends between at least a region underneath the first trench isolation structure and a region underneath the first spaced-apart region. The n-well region is contiguous with the p-well region and includes third and fourth spaced-apart n-regions, a channel region between the third and fourth spaced-apart regions, a second trench isolation structure contiguous with the third spaced-apart region, and an n-type doped diffused region extending between at least a region underneath the second trench isolation structure and a region underneath the third spaced-apart region.
Further in accordance with the invention, there is provided a method for forming a buried guard ring. The method includes the steps of forming a plurality of shallow trenches, providing a first photoresist over the substrate, patterning and defining the photoresist, implanting the substrate with a dopant to form a diffused region, and removing the photoresist. The method also includes the steps of oxidizing the substrate to grow oxides inside the plurality of shallow trenches, forming an MOS device over the substrate, which comprises the steps of forming spaced-apart regions and forming a gate structure including a gate electrode and a gate insulator having spacer oxides, and implanting heavy dopants into the diffused region and the spaced-apart regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4599789 (1986-07-01), Gasner
patent: 5296392 (1994-03-01), Grula et al.
patent: 5369595 (1994-11-01), Gould et al.
patent: 5770504 (1998-06-01), Brown et al.
patent: 5888881 (1999-03-01), Jeng et al.
patent: 5976939 (1999-11-01), Thompson et al.
patent: 5989977 (1999-11-01), Wu
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Pham Long
Winbond Electronics Corporation
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