Chemistry: analytical and immunological testing – Optical result – With reagent in absorbent or bibulous substrate
Reexamination Certificate
1998-11-25
2002-08-13
Niebling, John F (Department: 2812)
Chemistry: analytical and immunological testing
Optical result
With reagent in absorbent or bibulous substrate
C438S960000
Reexamination Certificate
active
06432724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor circuits, and more particularly to substrates having buried ground planes and their method of processing.
2. Description of the Related Art
As improved technology is developed, the size of semiconductor components, and correspondingly the size of end-product equipment in which they are used, continues to decrease. This has led to the concept of a “system on a chip.” This concept of a “system on a chip” has been around since the very large scale integration (VLSI) era. As integrated circuit technology enters the ultra large scale integration (ULSI) era, the desire for a “system on a chip” is increasing.
The concept of a system on a chip refers ideally to a computing system in which all the necessary integrated circuits are fabricated on a single wafer or substrate, as compared with today's method of fabricating many chips of different functions, i.e., logic and memory, and connecting them to assemble a system. There are problems, however, with the implementation of a truly high performance system on a chip because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits. To overcome some of these problems, a “system module” has been developed. A system module may consist of two chips, i.e., a logic chip and a memory chip, with one stacked on the other in a structure called Chip-on-Chip (COC) using a micro bump bonding (MBB) technology. The resulting dual-chip structure is mounted on a silicon substrate. Additional components and chips may also be mounted on the silicon substrate.
The multiple chips mounted on the single substrate in a system module typically include different circuits, i.e., some analog circuits and some digital circuits. This requires a low impedance ground in the system module to suppress digital noise that may appear in the analog circuits of these mixed mode circuits. Digital noise is the side effect of the switching of the logic circuits. High-speed synchronous digital integrated circuits require large switching currents which can induce noise on the power distribution networks and ground busses due to the finite resistance and inductance in these circuits. The noise may consist of voltage spikes appearing at the power supply terminals of the chip with the switching activity. Power supply noise can have a significant effect due to simultaneous switching noise in CMOS integrated circuits. These problems are more severe in mixed-mode circuits and require careful design of the power distribution systems.
Thus, a silicon substrate with a low impedance built-in ground plane is necessary for the system modules to suppress noise. It is also desirable for a built-in ground plane to be planar with the surface of the substrate to maintain a flat surface on the substrate upon which various chips, active circuits, and passive components (such as decoupling capacitors and termination resistors) can be subsequently mounted. A conventional method for forming buried conductors in a substrate is the use of heavy ion implantation of conducting atoms into the substrate to form the conductor. This approach, however, is not economically viable due to the required high-current, high-energy implanters, and may also cause damage to the overlying substrate. Another conventional method for fabricating a multilevel interconnect is to implant silicon into silicon oxide followed by a selective deposition of tungsten to build a multi-layer structure with low electrical resistivity. This method, however, is suitable only for fabricating a buried conductor in a silicon oxide, and not in a silicon substrate as is required in a system module.
Thus, there exists a need for an apparatus and method for simply and inexpensively fabricating a buried ground plane in a silicon substrate for use in multi-chip system modules.
SUMMARY OF THE INVENTION
The present invention provides a simple and low-cost scheme for producing a buried ground plane in a silicon substrate. In accordance with the present invention, the desired conductors are patterned by ordinary lithography on the surface of the silicon substrate in a mesh pattern to leave room for other chips and components to be mounted. A porous structure is produced only in the patterned conductors by depositing silicon nitride windows on the silicon and subjecting the wafer to a chemical anodization process. After the formation of the pores, the pores are then filled with a conductive metal by the use of a selective deposition technique. The filled pores may be subjected to a high-temperature annealing process to convert the deposited conductive metal to a metal silicide.
REFERENCES:
R.L. Smith, “Applications of Porous Silicon to Microstructure Fabrication”, The Electrochemical Society Proceedings, Vol. 94-32, 1994, pp. 281-288.*
T. Mimura et al., “System module: a new Chip-On-Chip module technology,” Proc. of, IEEE 1997 Custom Integrated Circuit Conf., pp. 439-442, 1997.
R.J. Jensen et al., “Mission: MCM, Designing for Reliability in Harsh Environments”, Advanced Packaging, Jan., 1998, pp. 22-26.
M. Gribbons et al., “Finite-Difference Time-Domain Analysis of Pulse Propagation in Multichip Module Interconnects”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16, No. 5, Aug. 1993, pp. 490-497.
R. Downing et al., “Decoupling Capacitor Effects on Switching Noise”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16, No. 5, Aug. 1993, pp. 484-489.
D.C. Thomas et al., “A Multilevel Tungsten Interconnect Technology”, Digest of 1988 IEDM, 1988, pp. 466-469.
V.M. Dubin et al., “Porous Silicon: Metal Plating and Anodic Oxidation”, The Electrochemical Society Proceedings, vol. 94-32, 1994, pp. 299-311.
R. Herino et al., “Nickel Plating on porous Silicon”, J. Electrochem. Soc., Oct. 1985, pp. 2513-2514.
R.L. Smith, “Applications of Porous Silicon to Microstructure Fabrication”, The Electrochemical Society Proceedings, vol. 94-32, 1994, pp. 281-288.
S.S. Tsao et al., “Tungsten deposition on porous silicon for formation of buried conductors in single crystal silicon”, Appl. Phys. Lett. vol. 49, No. 7, Aug. 18, 1986, pp. 403-405.
R.S. Blewer et al., “Tungsten Depostions on Porous Silicon for the Formation of Buried Layer Conductors”, Tungsten and Other Refractory Metals for VLSI Applications II, Proc. of 1986 Workshop, Ed. By E.K. Broadbent, materials research Society, 1987, pp. 401-407.
K-M Chang et al., “Influences of damage and contamination from reactive ion etching on selective tungsten depositions in a low-pressure chemical-vapor deposition reactor”, J. Appl. Phys. vol. 80, No. 5, Sep. 1, 1996, pp. 3056-61.
A. Kobayashi et al., “The deposition rate for Cu-CVD with Cu(hfac)(tmvs)” Advanced Metallization and Interconnect systems for ULSI applications, Conference Proceedings ULSI XII, Materials research Society, 1997, pp. 177-183.
Ahn Kie Y.
Forbes Leonard
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Niebling John F
Zarneke David A
LandOfFree
Buried ground plane for high performance system modules does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buried ground plane for high performance system modules, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buried ground plane for high performance system modules will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2913084