Buried channel type transistor having a trench gate and...

Details Buried channel type transistor having a trench gate and... Buried channel type transistor having a trench gate and...

2006-06-13

2006-06-13

Wojciechowicz, Edward (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S306000, C257S328000

Reexamination Certificate

active

07060574

ABSTRACT:
In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to a sidewall of the trench, respectively. A gate electrode filling the trench is formed. Source/drain regions are formed at portions of the substrate adjacent to the sidewall of the gate electrode. Stopper regions are formed at portions of the substrate beneath the source/drain regions and beneath the first and second threshold voltage control regions, respectively. The buried channel type transistor has a high breakdown voltage between the source/drain regions although a threshold voltage thereof is low.

REFERENCES:
patent: 5620911 (1997-04-01), Park
patent: 5828100 (1998-10-01), Tamba et al.
patent: 5828103 (1998-10-01), Hsu
patent: 6316806 (2001-11-01), Mo
patent: 2002/0038886 (2002-04-01), Mo
patent: 2001-339063 (2001-12-01), None
patent: WO 02/057506 (2002-07-01), None
English language Abstract from WO patent publication No. WO 02/057506 A2.
English Language Abstract from Japanese patent publication No. JP2001-339063.

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