Buried channel PMOS transistor in dual gate CMOS with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S224000, C438S227000, C438S306000, C438S532000

Reexamination Certificate

active

06514810

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistors and more specifically to a novel process to form a buried channel PMOS transistor in a dual gate CMOS technology with reduced mask steps.
BACKGROUND OF THE INVENTION
As more functions become integrated on a single chip it is often necessary for analog and digital signals to be processed on the same chip. Integrated circuits that process both analog and digital signals are commonly referred to as mixed signal circuits. The MOS transistor is the building block of most integrated circuits and MOS transistors with different properties will be required to processing digital and analog signals.
Switching speed is often the most important property for a MOS transistor that processes digital signals while low noise is more important for analog signals. These differing transistor properties will require different processing conditions to produce the optimum transistor for each application. The properties of the MOS transistors depend on the gate oxide thickness, the length and width of the gate, and the doping profiles that form the various regions of the transistor. For a given gate oxide thickness, the doping profiles will be used to optimize the MOS transistor for digital or analog signal processing. The doping profiles for the various transistors are formed using ion implantation and photolithography.
Current integrated circuit manufacturing technology uses photolithography to form masks on the silicon substrate during the manufacture of the integrated circuit. These masks allow for the selective doping of the various layers used to form the integrated circuit using ion implantation. The formation of each layer of masks requires a process of depositing photoresist, exposing the photoresist to light through a photomask, and removing exposed or non exposed areas of the photoresist leaving a patterned film on the surface of the substrate. This photolithography process adds tremendous cost to the fabrication of the integrated circuit and it is therefore important that the number of photomasks that are used during the fabrication process be kept at a minimum.
SUMMARY OF THE INVENTION
The instant invention comprises a method for forming a buried channel PMOS transistor for analog applications. In particular, the method comprises forming a third well region in the semiconductor substrate by simultaneously forming a n-well region and a third well region in said semiconductor substrate by implanting n-type dopants into said substrate and forming a p-well region in said semiconductor substrate by implanting p-type dopants into said semiconductor substrate wherein said third well region is simultaneously implanted with said p-type dopants.
A dielectric layer is formed over the third well region and a gate layer is formed over the dielectric layer to form the gate stack of the buried channel PMOS transistor. The buried channel PMOS transistor is completed using the same implant processes used to form the various regions of the CMOS transistors used to process digital signals.
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 5693505 (1997-12-01), Kobayashi
patent: 5702988 (1997-12-01), Liang
patent: 5817551 (1998-10-01), Fujii et al.
patent: 5937287 (1999-08-01), González
patent: 6211003 (2001-04-01), Taniguchi et al.

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