Buried-channel MOS transistor and process of producing same

Details Buried-channel MOS transistor and process of producing same Buried-channel MOS transistor and process of producing same

1996-11-12

1998-02-17

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257346, 257387, 257404, 257408, H01L 2976, H01L 2994, H01L 31062

Patent

active

057194300

ABSTRACT:
In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. Then p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle section. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

REFERENCES:
patent: 5329138 (1994-07-01), Mitani et al.
Adele E. Schmitz, Prahalad K. Vasudev and John & Chen, "High Performance Subhalf-Micrometer P-Channel Irnasistors for CMOS VLSI" IEEE Technical Digest (1984), pp. 423-426.
C. Mazure, R. Subrahmanyan, C. Gunderson and M. Orlowski, "Design Considerations For Sub-0.35 .mu.m Buried Channel P-MOSFET Devices", IEEE VLSO Symposium, Digest of Technical Papers, (1992) pp. 92-93.

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