Buried biasing wells in FETs (Field Effect Transistors)

Details Buried biasing wells in FETs (Field Effect Transistors) Buried biasing wells in FETs (Field Effect Transistors)

2007-08-27

2010-06-08

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S372000, C257SE29054

Reexamination Certificate

active

07732286

ABSTRACT:
A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.

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