Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-12-24
2002-04-30
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S673000, C257S780000, C257S782000
Reexamination Certificate
active
06380555
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and testing. More particularly, this invention relates to a bumped semiconductor component having test pads, and to a method and system for testing bumped semiconductor components.
BACKGROUND OF THE INVENTION
Semiconductor components, such as bare semiconductor dice, semiconductor packages, chip scale packages, BGA devices, and semiconductor wafers can include terminal contacts in the form of bumps. This type of component is sometimes referred to as a “bumped” component (e.g., bumped die, bumped package, bumped wafer).
FIGS. 1 and 1A
illustrate a bumped semiconductor component which comprises a “flip chip” semiconductor package
10
. The package
10
includes a semiconductor die
12
, and an array of bumped contacts
14
bonded to a face
16
(circuit side) of the die
12
. The bumped contacts
14
allow the package
10
to be surface mounted to a mating substrate, such as a printed circuit board (PCB) Typically, the bumped contacts
14
are made of solder, such that the package
10
can be bonded to the mating substrate using a solder reflow process. In addition, the bumped contacts
14
can be arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA), to provide a high input/output capability for the package
10
. Further, the bumped contacts
14
can have a spherical, hemispherical, conical, dome or other shape.
The die
12
contained in the package
10
includes a pattern of die contacts
20
(e.g., bond pads) in electrical communication with the bumped contacts
14
. In addition, the die
12
includes internal conductors
22
in electrical communication with the die contacts
20
, and with various semiconductor devices and integrated circuits formed on the die
12
. The die
12
also includes a passivation layer
24
formed on the face
16
of the die
12
, and openings
26
through the passivation layer
24
to the die contacts
20
. Typically, the passivation layer
24
comprises a glass, such as borophosphosilicate glass (BPSG), an oxide, such as SiO
2
, or a polymer, such as polyimide.
The die
12
also includes a redistribution circuit
32
formed on a surface
34
of the passivation layer
24
, which interconnects the bumped contacts
14
to the die contacts
20
. The redistribution circuit
32
includes a pattern of conductors
36
in electrical communication with the die contacts
20
, and an outer passivation layer
38
which covers the conductors
36
. The conductors
36
can have a “fan out” configuration to provide a required pitch and pattern for the bumped contacts
14
.
Redistribution circuits are typically used in semiconductor manufacture to “fan out” the signals from standard wire bond pads, to pads of a dense area array, such as a ball grid array (BGA). In an ideal situation, the die
12
would be designed to have the die contacts
20
in a pattern that does not require the redistribution circuit
32
to be added. For example, a semiconductor manufacturer can design the die
12
and the die contacts
20
such that the die contacts
20
are already in a grid array, for attaching solder balls of a ball grid array (BGA). However, as this ideal situation does not always exist, redistribution circuits are widely used in semiconductor manufacture.
The outer passivation layer
38
of the redistribution circuit
32
insulates the conductors
36
, and helps to locate the bumped contacts
14
. In addition, the outer passivation layer
38
functions as a solder mask to prevent solder from flowing between the bumped contacts
14
during attachment of the bumped contacts
14
, and during surface mounting of the package
10
. The outer passivation layer
38
can comprise a dielectric material. Suitable materials for the outer passivation layer
36
include polymers such as polyimide, glasses, such as BPSG, or oxides, such as SiO
2
. The outer passivation layer
38
includes openings
40
, and the bumped contacts
14
are located within the openings
40
, and bonded to the conductors
36
. As shown in
FIG. 1B
, the redistribution circuit
32
can also include an under bump metallization layer (UBM)
44
, for each bumped contact
14
to facilitate bonding to the conductors
36
.
For performing test procedures on the package
10
it is necessary to make temporary electrical connections with the bumped contacts
14
. Different types of interconnects have been developed for making these temporary electrical connections.
One type of interconnect, typically used for testing components at the wafer level, is known as a “probe card”. Probe cards are typically utilized to test dice contained on a semiconductor wafer prior to dicing of the wafer into individual dice. Probe cards can also be used to test other semiconductor components, such as the packages
10
contained on a wafer, on a panel, or on leadframe.
A needle probe card includes contacts in the form of needle probes
42
(
FIG. 1A
) which are configured to electrically engage the bumped contacts
14
. Another type of probe card, manufactured by Wentworth Labs of Brookfield, Conn., is known as a “COBRA” probe card, and includes contacts in the form of buckle beams. Another type of probe card, manufactured by Form Factor, of Elmsford N.Y. includes contacts in the form of wires shaped as spring segments. Still another type of probe card, as described in U.S. Pat. No. 5,894,161 to Akram et al., includes silicon contacts covered with a conductive layer.
In addition to probe cards, another type of interconnect is used to test singulated components. For example, for testing singulated components such as dice or packages, the interconnect can be contained within a carrier adapted to temporarily package one or more components. U.S. Pat. Nos. 5,896,036; 5,844,418; and 5,878,485 to Wood et al.; U.S. Pat. No. 5,783,461 to Hembree; and U.S. Pat. No. 5,815,000 to Farnworth et al. describe carriers for singulated components.
With these carrier-type interconnects, the contacts can comprise projections configured to penetrate the bumped contacts
14
, or alternately indentations configured to retain the bumped contacts
14
. U.S. Pat. No. 5,894,161 to Akram et al. and U.S. Pat. No. 5,962,291 to Farnworth et al. describe this type of interconnect.
Regardless of the type of interconnect, problems can arise in making the temporary electrical connections with the bumped contacts
14
. For example, bumped contacts
14
formed of a relatively soft material, such as solder, tend to produce flakes during testing. These flakes can contaminate the equipment used to conduct the test procedures. In addition, solder, and contaminants attracted to the solder, can build up on the interconnect contacts. This build up can increase electrical resistivity through the contacts, and adversely affect the test procedures. Needle probes
42
(FIG.
1
A), for example, can only be used for several hundred touch downs on bumped contacts
14
formed of solder before they require cleaning.
Another problem during testing of bumped components, particularly with bumped contacts
14
formed of solder, is that the bumped contacts
14
deform easily during handling and testing, especially at elevated temperatures. For performing test procedures, it may be difficult to make low resistance electrical connections with deformed bumped contacts
14
. Also for subsequent bonding procedures, the deformed bumped contacts
14
can make alignment and bonding of the component to a mating substrate more difficult. In addition, deformed bumped contacts
14
are a cosmetic problem that can adversely affect a users perception of a semiconductor component. Still further, the bumped contacts
14
can be separated from the component
10
during electrical engagement by the interconnect contacts.
In view of the foregoing problems associated with testing bumped semiconductor components, improved bumped semiconductor components capable of being more easily tested, are needed in the art. Also needed are improved test procedures and test systems for testing bumped semico
de Varona Jorge L.
Hembree David R.
Forde Remmon R.
Gratton Stephen A.
LandOfFree
Bumped semiconductor component having test pads, and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bumped semiconductor component having test pads, and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bumped semiconductor component having test pads, and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2900727