Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2002-04-10
2004-11-16
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S784000, C257S738000, C257S691000, C257S692000, C257S693000, C257S696000, C257S698000, C257S786000, C257S737000, C257S796000
Reexamination Certificate
active
06818976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a method for manufacturing the same. More particularly, the present invention relates to a bumped chip carrier package using a lead frame and a method for manufacturing the same.
2. Description of the Related Art
In an effort to reduce the size and weight of multi-function electronic devices while simultaneously increasing speed and performance, high-density integrated circuits (ICs) are being mounted in high-density packages. One such high-density package is a chip scale package (CSP), wherein ICs are mounted directly on a substrate. Although such CSPs have been manufactured in sizes as small as a single IC, a CSP may provide for the mounting of multiple ICs on a common substrate or carrier, such as a printed circuit board (PCB), a tape circuit board, or a lead frame. One such conventional CSP is a bumped chip carrier (BCC) package, which uses a lead frame as shown in
FIGS. 1 through 3
, wherein
FIG. 2
illustrates a cross-sectional view taken along line
2
—
2
in FIG.
1
.
Referring to the two views of the BCC package shown in
FIGS. 1 and 2
, a semiconductor chip
20
is attached to a chip mounting area
12
of a lead frame
10
, and a plurality of contact grooves
14
are formed around the periphery of the chip mounting area
12
. Each one of a plurality of bonding pads
24
on semiconductor chip
20
are electrically connected to an associated contact groove
14
by a bonding wire
30
. The semiconductor chip
20
, the plurality of bonding wires
30
, and the plurality of contact grooves
14
on lead frame
10
are then encapsulated with a molding resin to form a resin mold
40
.
Each contact groove
14
typically includes a depression having an overlaying plating layer
16
, which is formed by successive deposition and/or etching of metal layers using metals, such as stannum (Sn), palladium (Pd), and aurum (Au). Since it is difficult to attach a bonding wire
30
directly to the concave plating layer
16
, a conventional procedure for connecting the bonding wire
30
to the plating layer
16
is typically a two-step process.
In a first step, a first plurality of ball solder bumps
32
are formed on each one of the contact locations on plating layer
16
using a ball bonding technique. A second plurality of ball solder bumps are then formed on each one of the bonding pads
24
of semiconductor chip
20
. A stitch bonding operation is then performed to connect each end of the bonding wires
30
to the associated ball solder bumps.
An alternate variation on this conventional CSP might feature the elimination of lead frame
10
under the resin mold
40
by using a selective etching, such as that shown by the conventional bumped chip carrier package
50
of FIG.
3
. In bumped chip carrier package
50
, an external contact terminal
18
has a structure in which plating layer
16
is filled with a molding resin.
Because the height of the external contact terminals
18
in the bumped chip carrier package
50
may be adjustably controlled during the manufacturing process of the lead frame, the bumped chip carrier package
50
has a significant advantage over conventional semiconductor chip mounting techniques using conventional solder balls as an external contact terminal.
Disadvantageously, however, since a conventional external contact terminal structure features a plating layer
16
being filled with a molding resin, plating layer
16
may exhibit cracking due to a difference in thermal expansion coefficients between the plating layer
16
and the molding resin during conventional manufacturing tests of bumped chip carrier package
50
, for example, during a temperature cycling (T/C) test. Another significant disadvantage of conventional CSPs is that the aforementioned two-step ball bonding operation is typically required in the wire bonding process.
SUMMARY OF THE INVENTION
In an embodiment of the present invention, a bumped chip carrier (BCC) package is manufactured to use a lead frame capable of preventing damage to an external contact terminal during manufacturing testing.
A feature of an embodiment of the present invention provides a BCC package using a lead frame capable of electrically connecting a semiconductor chip and an internal contact terminal using a single wire bonding process.
According to an aspect of an embodiment of the present invention, a method for manufacturing a bumped chip carrier package is provided which includes, (a) providing a lead frame having a chip mounting area and a plurality of internal contact terminals protruding from the lead frame beyond the chip mounting area, (b) attaching a semiconductor chip having a plurality of bonding pads to the chip mounting area, (c) electrically connecting each one of the plurality of bonding pads of the semiconductor chip to an associated one of a plurality of internal contact terminals using one of a plurality of bonding wires, (d) forming a resin mold by encapsulating the semiconductor chip, the plurality of bonding wires, and the plurality of internal contact terminals on the lead frame with a molding resin, and (e) forming a plurality of external contact terminals by removing the lead frame except for a portion under each one of the plurality of internal contact terminals.
In the above method, (a) may additionally include (a1) providing a lead frame, (a2) forming a first photoresist pattern at a plurality of locations associated with the locations for formation of the plurality of internal contact terminals on the lead frame, (a3) forming the plurality of internal contact terminals by wet etching the lead frame assembly outside of the first photoresist pattern to a predetermined depth, and (a4) removing the first photoresist pattern.
Further, (e) may additionally include (e1) forming a second photoresist pattern under the lead frame such that a plurality of openings are created, each of the plurality of openings being located under one of the plurality of internal contact terminals, (e2) forming a plurality of solder plating layers, each one being formed in an associated one of the plurality of openings in the second photoresist pattern, (e3) removing the second photoresist pattern, (e4) removing the lead frame located outside of the plurality of solder plating layers by using the plurality of solder plating layers as masks, and (e5) forming the plurality of external contact terminals by re-flowing the plurality of solder plating layers, such that the lead frame under each one of the plurality of solder plating layers are covered with solder.
Preferably, each one of the plurality of openings in the second photoresist pattern is formed to a size sufficient to include at least one of the plurality of internal contact terminals.
According to another aspect of an embodiment of the present invention, a bumped chip carrier package includes a semiconductor chip on which at least one bonding pad is formed, at least one lead frame terminal arranged close to the semiconductor chip, wherein a lower portion of the lead frame terminal is located beneath a bottom side of the semiconductor chip, at least one bonding wire electrically connecting the bonding pad to the lead frame terminal, and a resin mold formed by encapsulating the semiconductor chip, the bonding wire, and an upper portion of the lead frame terminal with a molding resin, wherein the resin mold is formed so the bottom side of the semiconductor chip is externally exposed.
Additionally, the lead frame terminal includes at least one internal contact terminal located internally to the resin mold, at least one bonding wire connected between the internal contact terminal and the bonding pad of the semiconductor chip, and at least one solder-plated external contact terminal formed under the internal contact terminal and extending beyond the resin mold so that the external contact terminal is located below the bottom side of the semiconductor chip.
Preferably, a middle portion of the internal contact terminal is formed having a constricted shap
Ahn Sang Ho
Kang In Ku
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
Williams Alexander Oscar
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