Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1997-10-16
1999-10-05
Dutton, Brian
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438439, H01L 2176
Patent
active
059638176
ABSTRACT:
A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.
REFERENCES:
patent: 5670412 (1997-09-01), Juengling
patent: 5783498 (1998-07-01), Dotta
Solid State Phenomena, vols. 47-48 (1996), pp. 17-32, Scitec Publications, Switzerland 1996.
Chu Jack Oon
Ismail Khalid EzzEldin
Lee Kim Yang
Ott John Albrecht
Dutton Brian
International Business Machines - Corporation
Trepp Robert M.
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