Built-in test for multiple memory circuits

Details Built-in test for multiple memory circuits Built-in test for multiple memory circuits

2005-09-06

2005-09-06

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S736000, C714S025000

Reexamination Certificate

active

06941494

ABSTRACT:
A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.

REFERENCES:
patent: 6044481 (2000-03-01), Kornachuk et al.
patent: 6088823 (2000-07-01), Ayres et al.
patent: 6263461 (2001-07-01), Ayres et al.
patent: 6510530 (2003-01-01), Wu et al.
patent: 6567325 (2003-05-01), Hergott
patent: 6587979 (2003-07-01), Kraus et al.
patent: 6694461 (2004-02-01), Treuer
M. Lobetti-Bodoni et al., “An Effective Distributed BIST Architecture for RAMs”, May 23-26, 2000, IEEE European Test Workshop, pp 119-124.
U.S. Appl. No. 09/679,209, Andreev et al.
U.S. Appl. No. 09/679,313, Andreev et al.

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