Built in self test transport controller architecture

Details Built in self test transport controller architecture Built in self test transport controller architecture

2006-11-08

2009-06-09

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S734000

Reexamination Certificate

active

07546505

ABSTRACT:
A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.

REFERENCES:
patent: 5325367 (1994-06-01), Dekker et al.
patent: 6011748 (2000-01-01), Lepejian et al.
patent: 6885599 (2005-04-01), Saitoh et al.

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