Built in self test system and method for detecting and...

Details Built in self test system and method for detecting and... Built in self test system and method for detecting and...

2004-06-25

2008-08-05

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

07409616

ABSTRACT:
A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a bit has slipped, then the built-in-self test mechanism can also implement either a clock generation stretch operation or a barrel shift operation to readjust the frame boundary output from a receiver with a 1-to-N deserializer. A pseudo-random bit sequence can be generated having the same logic value in both the receiver and transmitter, where the output of the deserializer which receives the transmitted bits is compared bit-by-bit with the receiver-generated bits as part of the built-in-self test mechanism. If a bit is determined to have been slipped, then error correction occurs with aliasing and phase jitter in mind.

REFERENCES:
patent: 5128940 (1992-07-01), Wakimoto
patent: 5502748 (1996-03-01), Wilkinson
patent: 5790563 (1998-08-01), Ramamurthy et al.
patent: 6078937 (2000-06-01), Vatinel
patent: 6459393 (2002-10-01), Nordman
Lin et al., A BIST Methodology for At-Speed Testing of Data Communications Transceivers, Dec. 4-6, 2000, IEEE, pp. 216-221.

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