Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-05
2010-11-23
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
07840865
ABSTRACT:
A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.
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Cheng Wu-Tung
Lai Liyang
Rinderknecht Thomas Hans
Kerveros James C
Klarquist & Sparkman, LLP
Mentor Graphics Corporation
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