Built-in self test for multiple memories in a chip

Details Built-in self test for multiple memories in a chip Built-in self test for multiple memories in a chip

1999-03-16

2002-03-19

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S730000, C714S733000

Reexamination Certificate

active

06360342

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a new built-in self-testing (BIST) architecture for multiple memories with different sizes (different address width or different word _width) in a chip.
2. Description of the Prior Art
Traditionally, most of the testing methods of memories are limited to single memory or memories with the same sizes.
According to the report “Serial Interfacing for Embedded Memory Testing” by B. N. Dostie et al., in IEEE Design & Test of Computers, 1990, pp.52-63, built-in self-testing architecture can be applied in the testing of multiple memories with different sizes. The main characteristic is that the flip-flops in the input/output ports of each memory with different sizes are connected in series and form a scan chain. i.e., all memories with different sizes can be regarded as a large memory. The testing time of this method is very long. L. Ternullo et al. reported another testing method of built-in self-test (BIST) architecture for multiple memories with different sizes in “Deterministic Self-Test of A High-Speed Embedded Memory and Logic Processor Subsystem” in Proceedings of
Int. Test Conf.
PP. 33-44(1995). The main characteristic is that all memories to be tested share the same address generator, and each memory has its own data generator and output comparator. But, the extra area needed for this method is quite large.
The U.S. Pat. No. 5,388,104 patent demonstrated another testing method of built-in self-test architecture for multiple memories with different sizes. The main characteristic is that all memories to be tested share the same counter-based address generator, and each memory also has its own data generator and output comparator. The extra area needed for this method is also quite large.
SUMMARY OF THE INVENTION
The present invention is the design of a new built-in self-test (BIST) architecture for multiple memories with different sizes in a chip to resolve the above problems. All memories to be tested share the same address generator, which is implemented by a linear feedback shift register. In the portion of output comparison, the registers in the input/output port of each memory with different sizes are connected in series and form a scan chain, and then connected to the data input signal provided by the built-in self-test (BIST) controller in parallel. Therefore, the testing time of this method is shorter; and the extra area needed for this method is quite small. During the testing process, the small memory will be tested first and then turned off by the built-in self-test (BIST) controller, so the total testing power consumption will be decreased.


REFERENCES:
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5388104 (1995-02-01), Shirotori et al.
International Test Conference, Ternullo, Jr. et al, 1995, “Deterministic Self-Test of a High-Speed . . . ”, pp. 33-44.

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