Built-in self test for memory arrays using error correction...

Details Built-in self test for memory arrays using error correction... Built-in self test for memory arrays using error correction...

2007-08-07

2007-08-07

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10931709

ABSTRACT:
A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations. The test control circuit provides a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.

REFERENCES:
patent: 4001818 (1977-01-01), Radichel et al.
patent: 5841785 (1998-11-01), Suzuki
patent: 5896398 (1999-04-01), Sekine
patent: 6550023 (2003-04-01), Brauch et al.
patent: 6738938 (2004-05-01), Nadeau-Dostie et al.
patent: 7134063 (2006-11-01), Cho et al.
patent: 2004/0107396 (2004-06-01), Barone et al.
patent: 2004/0205427 (2004-10-01), Ichikawa
patent: 2006/0041799 (2006-02-01), Sato

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