Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-06-20
1996-10-22
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Testing
36518907, 371 211, G11C 700
Patent
active
055684378
ABSTRACT:
An integrated circuit with random access memory (RAM) and a built-in self tester for the RAM is disclosed. The built-in self tester includes a RAM BIST controller, a comparator, and a BIST I/O. The RAM BIST controller controls the RAM during a test where the RAM includes data, address, and control lines. The comparator is responsive to outputs of the RAM BIST controller and the RAM and develops an error signal. The BIST I/O is responsive to outputs of the comparator and has an output coupled to one of the I/O ports. The BIST I/O is further capable of storing an address of a data storage location in the RAM that malfunctions during the test and outputting the address via an integrated circuit I/O port.
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patent: 5132937 (1992-07-01), Tuda et al.
patent: 5278839 (1994-01-01), Matsumoto et al.
patent: 5327363 (1994-07-01), Akiyama
Dekker, Rob et al., "Fault Modeling and Test Algorithm Development for Static Random Access Memories," 1988 International Test Conference, IEEE, pp. 343-352.
Dinh Son T.
VLSI Technology Inc.
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