Built-in self test for content addressable memory

Details Built-in self test for content addressable memory Built-in self test for content addressable memory

2000-02-17

2003-04-15

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06550034

ABSTRACT:

TECHNICAL FIELD
This invention relates in general to a built-in self test for an integrated circuit, and in specific to a built-in self test for content adjustable memory.
BACKGROUND
Built-in self tests (BISTs) are commonly implemented within integrated circuits (e.g., chips) of the prior art to test the accuracy of such chips. For example, BISTs have been implemented in the prior art to allow for testing the accuracy of random access memory (RAM). However, many chips utilize content addressable memory (CAM). As is well known in the art, RAM memory, such as static RAM (SRAM) or dynamic RAM (DRAM), is commonly implemented for storing data. As is also well known in the art, a CAM structure is typically a RAM that comprises associated circuitry (e.g., a comparator) for comparing received data with data stored therein very quickly. As an example, cache structures implemented for processors typically include a translation look-aside buffer (TLB), which is generally a large CAM structure. Generally, when an instruction being executed by the processor requests access to memory (e.g., to read from or write to a memory address), the cache's TLB receives a virtual address for such memory access request and translates the virtual address to a physical address.
However, prior art designs have not implemented a BIST for testing a CAM structure. That is, a BIST for testing a CAM structure has not been utilized in prior art chips. Instead, CAM structures are typically tested in the prior art using off-chip software programs. Utilizing such off-chip testing programs of the prior art to test CAM structures typically requires a large amount of testing time. For example, an undesirably long time is typically required to test a TLB of the prior art.
In testing prior art chips that include CAM structures, a significant portion of the test time is typically required to test the CAM structure. For instance, testing a CAM structure utilizing testing procedures of the prior art may require thousands of clock cycles. As an example of a typical method used for testing a CAM structure, suppose a CAM structure is implemented on a chip for a TLB. To test the cells of the CAM used for the TLB, the entire CAM array may first be initialized to 0. Thus, the chip must be set into a mode in which a virtual address of all 0's can be input for each entry of the TLB. After each of the entries in the TLB are set to a virtual address of all 0's (e.g., virtual address =000000000), then a test address of all 0's and a walking 1 may be utilized to test the TLB's entries. For instance, a test address having a 1 only in its most significant bit position (e.g., test address 100000000) may be input to the TLB to ensure that the TLB does not translate this test address as matching with one of its entries (i.e., to ensure that a “miss” or “non-match” occurs for every entry of the TLB. If a “hit” (or “match”) is detected for any entry, then it is determined that the CAM structure failed (i.e., that the CAM structure is defective). After testing each entry for a test address having a 1 for its most significant bit position, the 1 is shifted or “walked” over to the next lower bit of the test address (e.g., test address=010000000) and is input to the TLB. The test is repeated on the TLB with the 1 being walked through each bit position of the test address, and if a “hit” (or “match”) is detected for any of the test addresses then it is determined that the CAM structure has failed.
Once the test has been completed for a walking 1, the test is typically repeated by initializing every cell of the CAM array to 1 and testing the CAM with a test address having all 1's and a walking 0. For example, each of the entries in the TLB may be set to a virtual address of all 1's (e.g., virtual address=111111111), then a walking 0 can be utilized to test the TLB's entries. For instance, a test address having a 0 only in its most significant bit position (e.g., test address=011111111) may be input to the TLB to ensure that the TLB does not translate this test address as matching with one of its entries (i.e., to ensure that a “miss” or “non-match” occurs for every entry of the TLB. If a “hit” (or “match”) is detected for any entry, then it is determined that the CAM structure failed (i.e., that the CAM structure is defective). After testing each entry for a test address having a 0 for its most significant bit position, the 0 is shifted or “walked” over to the next lower bit of the test address (e.g., test address=101111111) and is input to the TLB. The test is repeated on the TLB with the 0 being walked through each bit position of the test address, and if a “hit” (or “match”) is detected for any of the test addresses then it is determined that the CAM structure has failed.
Such a method of testing typically requires many clock cycles utilizing an off-chip testing program of the prior art. Accordingly, prior art CAM testing methods generally require an undesirably long time, which result in an overall longer production time. Additionally, because such off-chip testing requires a long time, the effective cost associated with producing and testing a chip of the prior art is undesirably high. Not only do prior art. CAM testing programs typically require an undesirably high number of clock cycles to complete, but such off-chip testing programs are typically serial clock tests that operate at approximately 10 megahertz (MHz). Thus, even if the processor speed of a chip is 500 MHz, the CAM testing is performed at approximately 10 MHz. As a result, prior art methods of performing CAM testing require an undesirably long time.
As discussed above, BISTs have been utilized for testing RAM structures of the prior art. However, such RAM BISTs are not readily capable of being implemented for CAM structures. That is, prior art RAM BISTs can not be implemented for CAM structures without making unobvious changes to such prior art RAM BISTs. Generally, RAM BISTs are not easily adapted as CAM BISTs because of the difference in the operation of a RAM structure and a CAM structure. For instance, during operation a RAM structure can typically have data written thereto and read therefrom. Accordingly, a RAM BIST typically writes data to the RAM structure, and then reads the data out of the RAM structure to ensure that the data read out is the same as the data that was written to the RAM.
However, the operation of a CAM structure is much different. That is, memory data can typically be written to a CAM structure, but generally it cannot be read from the CAM structure. Instead, the CAM structure typically receives data and compares it with memory data stored within the CAM. Typically, a CAM does not include circuitry for reading the actual memory data out of the CAM, but instead includes circuitry for comparing received data with the memory data stored therein to determine if a match is made. Because the memory data is not read out of the CAM, testing is typically more complicated for CAM structures than for RAM structures. For instance, testing CAM structures generally involves writing memory data to the CAM and then inputting various test patterns of data to ensure that the CAM structure correctly recognizes whether the input data matches an entry stored in the CAM. Such testing is generally more complex than the relatively simple method of writing memory data in and reading memory data out typically utilized in RAM structures.
Some CAM structures of the prior art include circuitry for reading out memory data That is, some CAM structures of the prior art include circuitry for reading out the actual memory data stored within the CAM. Therefore, the testing of such CAM structures is simplified and may be implemented much like testing methods of RAM structures (e.g., write memory data in and read memory data out). However, some testing is typically required for the CAM's compare circuitry to ensure that it recognized matches and mismatches in data. Also, the read circuitry implemented for suc

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