Built-in self test circuit for analog-to-digital converter...

Details Built-in self test circuit for analog-to-digital converter... Built-in self test circuit for analog-to-digital converter...

2006-11-27

2009-10-13

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C341S120000

Reexamination Certificate

active

07603602

ABSTRACT:
A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge circuit. The invention reduces the period of the signal under test, converts its pulse width to voltage and measures the output via an ADC. The clock jitter becomes sensitive through a delay cancellation method, thus, the accuracy is improved. The invention further comprises all testing procedure for period jitters of a PLL and static characteristics of an ADC. The test error caused by process variation can be corrected by a controllable delay circuit such that the error determination of the test result is prevented.

REFERENCES:
patent: 6456212 (2002-09-01), Kaplinsky
patent: 6492798 (2002-12-01), Sunter
patent: 7154421 (2006-12-01), Devendorf et al.
patent: 7208983 (2007-04-01), Imaizumi et al.
patent: 7375659 (2008-05-01), Huang

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