Built in self test BIST for RAMS using a Johnson counter as a so

Details Built in self test BIST for RAMS using a Johnson counter as a so Built in self test BIST for RAMS using a Johnson counter as a so

1997-10-24

2000-03-21

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714800, 714758, 714763, 365201, G11C 2900, G11C 700

Patent

active

06041426&

ABSTRACT:
Data or its inverse, is written into a regular structure, such as a RAM, while stepping through the address range. The data is then read out and a determination is made as to success or failure. The scheme is based upon a Johnson counter being the source of the data, or its inverse. This style of counting has the unique property that, every time a "count" takes place, the parity associated with the Johnson counter output will "toggle," since only one bit is allowed to change. Reliance on this parity toggling determines possible failures.

REFERENCES:
patent: 4061908 (1977-12-01), de Jonge et al.
patent: 5271015 (1993-12-01), Akiyama
patent: 5381373 (1995-01-01), Ohsawa
patent: 5475815 (1995-12-01), Byers et al.
patent: 5640354 (1997-06-01), Jang et al.
patent: 5689466 (1997-11-01), Quershi
patent: 5818772 (1998-10-01), Kuge

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