Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-07-06
2004-09-21
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S711000, C714S733000, C714S741000
Reexamination Certificate
active
06795942
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to the testing and repairing of semiconductor memory.
2. Description of Related Art
Semiconductor memory is a crucial resource in modern computers, being used for data storage and program execution. With the exception of the central processor itself, no other component within the computer experiences as high a level of activity. Traditional trends in memory technology are toward greater density (more memory locations, or “cells”, per part), higher speed and improved reliability. To some extent, these goals are inconsistent. For example, as memory density increases, the incidence of defects also rises. As a result, production yields of high-density memory devices with zero defects would be so low as to render them prohibitively costly. However, an alternative to building perfect devices is to build spare memory cells into the devices. After the memory is tested to locate any faults, any bad cells that were detected are replaced from among the spares. As long as there are sufficiently many working cells to replace the defective ones, a fully functional memory device can be made. Functional cells may be substituted for defective ones using a laser to restructure the interconnections within the memory device. Alternatively, the use of internal circuitry for self-test and self-repair is increasingly common in large memory devices. The techniques for internally detecting faulty memory cells and for replacing them with working cells are commonly referred to as built-in self-test (hereinafter, “BIST”) and built-in self-repair (hereinafter, “BISR”), respectively. BIST and BISR are instrumental in obtaining acceptable yields in the manufacture of high-performance semiconductor memory.
A typical memory device, as considered herein, is organized as m rows×n columns of regular (i.e., addressable) memory, along with p redundant rows (in which each row is n columns wide) and q redundant columns (in which each column is m rows deep). The use of redundant memory locations, together with on-chip circuitry for testing memory cells permits built-in self-test (BIST) of memory devices. Some memory devices also include built-in self-repair (BISR) circuitry, for reconfiguring internal connections. This allows redundant rows or columns to be substituted for defective regular rows or columns.
A memory test typically consists of writing a pattern to specific memory locations and then verifying that the written values were actually stored in those locations. If a particular cell is defective it will appear as a discrepancy in the pattern when it is read back. For example, a cell that cannot be written to will in effect be “stuck” at either a
1
or
0
, and an attempt to write the opposite value to that cell will fail and show up as an anomaly upon reading back the memory. Other failure modes may also occur, such as coupling errors, in which the logic state of a cell changes due to a change in an adjacent cell. A march technique is commonly used in testing memory. This technique involves first writing a test pattern to the memory, then starting at the top of the memory and marching through the addresses, reading the contents of each location, writing the opposite value, then moving on to the next address. A march can be rowfast or columnfast. A rowfast march takes one column and marches through it one row at a time, and a columnfast march does exactly the opposite.
BIST routines may perform effective self-test of the memory device, but do not prescribe a procedure for repair. The repair strategy requires determining how to allocate the available redundant rows and columns so that all defective cells are replaced. The larger the memory, the more formidable this task becomes.
The problem of optimizing the utilization of redundant rows and columns to repair the memory faults is known as “redundancy analysis”. Redundancy analysis of large memories is mathematically complex. Conventionally, an analysis of the entire addressable memory is performed by a dedicated memory tester, which utilizes complex mathematical algorithms to arrive at the optimal allocation of redundant rows and columns to repair all the defects. There are significant disadvantages associated with these testers. In the first place, they may be expensive. Since it is necessary to completely map the memory device and record the location of each defective cell before the tester can execute its repair algorithm, a substantial amount of memory is required within the tester itself. Moreover, the computationally intensive algorithm required for true optimal allocation of redundant rows and columns demands a substantial degree of processing power.
A further disadvantage to the use of conventional external memory testers is that the memory under test often may be embedded within another device (i.e., as on-chip memory), such as a microcontroller. In this case, the memory tester may not be capable of probing the memory directly. Then, the BIST feature of the memory is called upon to provide a bitmap to the tester by serially transmitting the information out through a single device pin. For large memory devices, this can clearly be a time-consuming process.
In view of the above-mentioned problems, it would be beneficial to have a more complete and robust method for self-test and self-repair of semiconductor memory devices.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a built-in redundancy analysis (hereinafter, BIRA) method suitable for inclusion in memory devices having built-in self-test (BIST) capability. It is assumed that the memory is organized as a matrix of rows and columns, comprising a regular portion and a redundant portion. It is further assumed that rows and columns from the redundant portion can be used to replace defective rows and columns in the regular portion. The method applies a multi-pass evaluation of the regular memory elements, where “element” refers to a row or column. In each pass, it records the number and location of defects in every regular element. If the number of defects in any element exceeds a threshold value, that element is flagged for replacement by one of the redundant elements. At this point, if the number of redundant elements available is greater than a predetermined acceptable value (preferably, zero), the number of available redundant elements is decremented and the process continues; however, if there are no remaining redundant elements to be used as replacements, the process terminates and the memory is designated non-repairable. At the conclusion of each pass through the memory the threshold value is decremented. If the threshold reaches zero, the process terminates and the memory is designated repairable; otherwise, the next pass begins. By lowering the threshold value with each pass, the criterion for replacement of defective memory elements becomes more and more stringent. This ensures that regular elements with the most defects are the first to be replaced, and is believed to lead to an efficient allocation of the redundant elements.
In a preferred embodiment, the regular memory elements comprise rows or columns of regular memory, and the redundant elements comprise redundant rows or columns. In a preferred embodiment, the present method employs both rowfast and columnfast marches, and uses a variety of test patterns. Alternate passes through memory perform column-wise, then row-wise evaluation, using one or more test patterns, which may vary. Following a successful test outcome, the addresses of rows and columns that need to be replaced can be scanned out of the memory, for use in laser repair; this takes far less time than scanning out a complete memory bitmap. Alternatively, if the memory device is capable of self-repair, redundant rows and columns can be swapped in automatically.
A system implementing the above-described BIRA method is also contemplated herein. In a preferred embodiment, the system may be comprised of standard logic gates
Conley & Rose, P.C.
Lamarre Guy J.
LSI Logic Corporation
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