Built-in fault testing of integrated circuits

Details Built-in fault testing of integrated circuits Built-in fault testing of integrated circuits

1992-05-01

1994-07-26

Snow, Walter E.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324500, 361 93, 371 51, 371 251, G01R 3100

Patent

active

053329732

ABSTRACT:
Built-in current mode quiescent current monitoring circuitry is provided for measuring a circuit's or a subcircuit's quiescent current. Anomalously high quiescent current (Iddq) generally results as a consequence of a manufacturing defect. These defects include those not detected by tests generated using traditional fault models. The technique provided here is based upon generating a proportionally matched current to the circuit under test current by a control loop. The proportionally matched current is then sent to a comparator where it is compared to a reference current, the reference current representing an acceptable quiescent current level. The output of the comparator then indicates whether the quiescent current is above or below the reference current.

REFERENCES:
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patent: 5023684 (1991-06-01), Tsunoda
patent: 5025344 (1991-06-01), Maly et al.
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patent: 5111136 (1992-05-01), Kawashima
Agarwal et al., Techniques for Implemention Large Area Devices-Elect Comp Eng-pp. 220, 221 & 224, Jan., 1986.
Carley et al., A Circuit Breaker For Redundant IC Systems-1988 Custom Integrated Circuits Conference pp. 27.6.1 & 27.6.5, Jan., 1988.
Feltham et al., Current Sensing for Built-In Testing of CMOS Circuits-Elect Comp Eng pp. 454 and 455, May 1988.

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