Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2011-06-14
2011-06-14
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230030, C365S148000
Reexamination Certificate
active
07961527
ABSTRACT:
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
REFERENCES:
patent: 7649788 (2010-01-01), Norman
patent: 2001/0007538 (2001-07-01), Leung
patent: 2006/0028864 (2006-02-01), Rinerson et al.
Hoang Huan
Unity Semiconductor Corporation
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