Buffer memory controller storing and extracting data of varying

Details Buffer memory controller storing and extracting data of varying Buffer memory controller storing and extracting data of varying

1996-12-12

1999-06-15

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

711109, 711212, 711219, 711220, 341 60, 341 67, 341101, G06F 912

Patent

active

059132299

ABSTRACT:
A buffer memory controller allows to sequentially store sampled data having variable bit length. That is, rather than assigning each sampled data to a single word of the memory, the sampled data is sequentially stored head to tail so that memory space is not wasted. The buffer memory controller includes: a sample pointer reading unit providing word addresses indicating the word position where the samples start, and a bit address indicating a bit position where the sample starts; a word shift register receiving data corresponding to the word addresses from the buffer memory, shifting the inputted data by the specific bit according to maximum assignable word, and outputting data of maximum assignable bit; a barrel shifter receiving the output of the shift register, shifting the inputted data by the bit address, and outputting the shifted data as maximum sample bit; and a masking circuit for inputting an output of the barrel shifter, masking the inputted data with mask data in accordance with each bit corresponding to the sample, and outputting the masked data as the maximum sample bit.

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IBM TDB, vol. 26, No. 10A, Mar. 1984, pp. 4912-4914.

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