Buffer memory circuit having constant propagation delay

Details Buffer memory circuit having constant propagation delay Buffer memory circuit having constant propagation delay

1991-10-29

1993-07-06

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518912, 36523008, G11C 1300

Patent

active

052260127

ABSTRACT:
A buffer memory circuit has a memory circuit for receiving input data possessing a transmission rate selected out of a plurality of predetermined transmission rates, a write-in clock signal synchronized with these input data and a read-out clock signal having a predetermined rate. The memory circuit stores the input data according to the write-in clock signal, and supplies the input data, which have been stored, as output data according to the read-out clock signal. A detecting circuit detects an overflow or an underflow in the memory circuit, and supplies a resetting pulse signal for initializing the memory circuit. A control circuit receives the write-in clock signal and the resetting pulse, and suspends the supply of the read-out clock signal to the memory circuit means for a certain period of time, determined by the first transfer rate, from the time of receiving the resetting pulse signal.

REFERENCES:
patent: 5083269 (1992-01-01), Syobatake et al.

Affiliated with

Also associated with

Rating

Buffer memory circuit having constant propagation delay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Buffer memory circuit having constant propagation delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer memory circuit having constant propagation delay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1695132