Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-10-09
1999-10-05
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711154, 711209, 711220, 711208, G06F 1200
Patent
active
059639776
ABSTRACT:
A method of coordinating access to a data buffer including a plurality of data blocks, using a buffer list with a plurality of entries corresponding to the data blocks. Each buffer list entry includes: (i) a status code for indicating the status of data in the corresponding data block, and (ii) a partial address common to both the next buffer list entry and a data block corresponding to said next buffer list entry. A status code is selected from a cyclical set of sequential status codes having a period of N, the status codes sequentially, and alternately, representing the most recent history of a data block, including: (i) full status, indicating data in the data block has been retrieved from the storage device or is to be stored to the storage device, or (ii) empty status, indicating data transferred out of the data block to a host or to the storage device. A store flag maintains a status code representing empty status, and a retrieve flag maintains a status code representing full status. When storing data into the data buffer, locating a desired buffer list entry list with an empty status code by traversing the buffer list, calculating the address of each entry using the partial address in the previous entry, until the desired entry is found. The address of the data block corresponding to the found entry is calculated and data is stored in the data block when the status code of the entry matches the store flag status code. The found entry status code is advanced once, and if the entry is last in the buffer list the store flag status code is advanced twice. Similarly, when retrieving data from the data buffer, locating a desired entry in the buffer list with a full status code by traversing the buffer list, calculating the address of each entry using the partial address in the previous entry, until the desired entry is found. The address of the data block corresponding to the found entry is calculated and data is retrieved from the data block when the status code of the entry matches the retrieve flag status code. The found entry status code is advanced once, and if the entry is last in the buffer list the retrieve flag status code is advanced twice.
REFERENCES:
patent: 5619673 (1997-04-01), Wang
patent: 5675765 (1997-10-01), Malamy et al.
patent: 5737757 (1998-04-01), Hassoun et al.
patent: 5764938 (1998-06-01), White et al.
patent: 5802546 (1998-09-01), Chisholm et al.
patent: 5812775 (1998-09-01), Van Seters et al.
patent: 5835925 (1998-11-01), Kessler et al.
patent: 5860119 (1999-01-01), Dockser
Yeon Seung Ryu et al., "Dynamic Buffer Management Technique for Minimizing the Necessity Buffer Space in a Continuous Media Server", Proceedings of Multimedia '96, pp. 181-185, 1996.
Kun-Lung Wu et al., "Consumption-Based Management Buffer for Maximizing System Throughout of Multimedia System", Proceedings of Multimedia '96, IEEE Transactions, pp. 164, 171, 1996.
David X. Chen et al., "A Buffer Management Scheme for the SCQQ Switch Under Nonuniform Traffic Loading", IEEE Transactions, pp. 2899-2907, 1994.
Bui Trinh
Gold Clifford M.
Li George
Luong Hoa
Mee Bryan
Bataille Pierre-Michel
Cabeca John W.
Quantum Corporation
Zarrabian Michael
LandOfFree
Buffer management and system coordination method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buffer management and system coordination method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer management and system coordination method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1183824