Buffer flush controller of a peripheral component interconnect-p

Details Buffer flush controller of a peripheral component interconnect-p Buffer flush controller of a peripheral component interconnect-p

1996-12-03

1999-11-09

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

395280, 395293, 395306, G06F 1300

Patent

active

059833041

ABSTRACT:
A buffer flush controller, of a peripheral component interconnect-peripheral component interconnect bridge (PPB), includes a first compounding circuit, a first state machine, a second state machine, and a second compounding circuit. The buffer flush controller can maintain data consistency by efficiently controlling a flush operation of a data buffer of a peripheral component interconnect bridge, and the buffer flush controller can ensure a normal system operation without deadlock.

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