Buffer control circuit and method for semiconductor memory devic

Details Buffer control circuit and method for semiconductor memory devic Buffer control circuit and method for semiconductor memory devic

1997-12-29

1999-07-27

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518908, G11C 1604

Patent

active

059301775

ABSTRACT:
A buffer control circuit and method for a semiconductor memory device with a power saving function power saving function. The buffer control circuit includes an internal clock signal generator for generating an internal clock signal in response to an external clock signal, an internal chip select signal generator for generating an internal chip select signal in response to an external chip select signal, a buffer control signal generator for combining the internal clock signal from the internal clock signal generator and the internal chip select signal from the internal chip select signal generator to generate a buffer control signal, a command/address buffering circuit operative in response to the buffer control signal from the buffer control signal generator, for storing external input command and address, and a decoder for decoding commands from the command/address buffering circuit. According to the present invention, the amount of current being consumed at a standby state of the semiconductor memory device can be reduced.

REFERENCES:
patent: 4970694 (1990-11-01), Tanaka et al.
patent: 5338978 (1994-08-01), Larsen et al.
patent: 5546021 (1996-08-01), Bizuneh et al.
patent: 5594704 (1997-01-01), Konishi et al.

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