Buffer circuit of semiconductor memory apparatus

Details Buffer circuit of semiconductor memory apparatus Buffer circuit of semiconductor memory apparatus

2009-06-30

2010-12-07

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S083000, C327S109000, C330S253000

Reexamination Certificate

active

07847592

ABSTRACT:
A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.

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patent: 2005/0140442 (2005-06-01), Tan
patent: 2008/0057279 (2008-03-01), Fang
patent: 10-0338928 (2002-05-01), None
patent: 20-0276958 (2002-05-01), None
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patent: 100422821 (2004-03-01), None

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