Buffer circuit

Details Buffer circuit Buffer circuit

1982-11-01

1984-08-21

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365227, 365233, 307450, G11C 700

Patent

active

044674554

ABSTRACT:
An input buffer circuit for a memory uses two transistors interposed between a push-pull pair of transistors to control the enabling of the buffer in response to a chip write signal generated from a logical combination of chip select and write enable signals. A plurality of inverters which provide complementary signals to the push-pull transistors are disabled and prevented from using current by an interrupt transistor until the interrupt transistor receives the chip write signal.

REFERENCES:
patent: 4275312 (1981-06-01), Saito et al.
patent: 4337523 (1982-06-01), Hotta et al.
patent: 4337525 (1982-06-01), Akatsuka
patent: 4384220 (1983-05-01), Segawa et al.
patent: 4385369 (1983-05-01), Sheppard
patent: 4387449 (1983-06-01), Masuda

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