Bridge-free self aligned silicide process

Details Bridge-free self aligned silicide process Bridge-free self aligned silicide process

1996-10-18

1998-07-21

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438230, 438649, 438651, 438655, H01L 2144

Patent

active

057834865

ABSTRACT:
A method of forming a transistor having silicide contacts to the gate and source/drain regions. A semiconductor substrate is provided having spaced field oxide regions and active areas. On the active areas, a gate structure is formed having a gate oxide, gate, and gate insulating layer. In an important step, the gate 18 is laterally etched to remove a first width of the gate. A second dielectric layer 22 composed of oxide is deposited over the sidewalls of the gate, the gate 18 and the substrate 10. The second dielectric layer 22 is etched forming sidewall spacers 24 on the sidewalls of the gate 18, the gate insulating layer 20, and the gate oxide layer. The gate insulating layer 20 is then removed with a selective etch. A metal layer 30 is deposited over the resulting surface. The metal layer 30 is heat treated forming a gate silicide contact 36 on the gate 18 and source and drain silicide contacts 34 on the active areas. The unreacted metal over the sidewall spacers and the field oxide regions is then removed with a selective etch. Impurity ions are implanted into the active areas forming source and drain regions 40 under the source and drain silicide contacts.

REFERENCES:
patent: 4786609 (1988-11-01), Chen
patent: 4818715 (1989-04-01), Chao
patent: 4885259 (1989-12-01), Osinski et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5612240 (1997-03-01), Chang
patent: 5627097 (1997-05-01), Venkatesan et al.

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