Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-23
2004-03-02
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06701475
ABSTRACT:
FIELD OF ART
The present invention relates to a boundary scan element used for a boundary scan testing method and a communication apparatus which applies the boundary scan element as a communication element thereto, more particularly to a boundary scan element for enabling high speed processing and a communication apparatus using the boundary scan element.
BACKGROUND OF THE INVENTION
Concerning a method for checking whether or not printed-wiring is correctly connected to corresponding IC chips and whether or not the printed-wiring is disconnected in a state where the IC chips are arranged on a wiring board on which the printed wiring is formed, a boundary scan testing method has been proposed.
The boundary scan testing method can be implemented for semiconductor integrated circuits (IC chips) in which the boundary scan elements are integrated. As shown in
FIG. 3
, the boundary scan element is composed, for example, of a plurality of boundary cells
214
, each of which is individually provided between an input/output terminal of an internal logic circuit
211
for allowing an integrated circuit
210
to achieve its inherent function and an input terminal
212
of the integrated circuit
210
as well as between the input/output terminal of the internal logic circuit
211
and an output terminal
213
of the integrated circuit
210
; a TAP controller (TAP circuit)
219
for controlling input/output of data to/from each boundary cell
214
; a TDI terminal
220
for receiving test data; a TDO terminal
221
for transmitting the test data; a TCK terminal
222
to which a clock signal is inputted; and a TMS terminal
223
for receiving a mode signal to switch an operation mode of the TAP controller
219
. Further, the boundary scan element may optionally be provided with any of a bypass register
215
; an ID CODE register
216
; an instruction register
217
; and a TRS terminal
224
for receiving a reset signal. The bypass register
215
serves to transfer communication data without allowing the communication data to pass through the boundary cells, and the ID CODE register
216
serves to discriminate sources of the communication data by outputting individually assigned ID CODES. The instruction register
217
serves to decode specified data selected among the communication data so as to perform a transition of the operation mode independently of a TMS signal. It should be noted that the bypass register
215
, the ID CODE register
216
and the instruction register
217
are called a boundary scan register (
118
).
Descriptions for terminals and signals inputted/outputted to/from the terminals will be made as follows. A TDI (Test Data In) is a signal for allowing instructions and data to be serially inputted to a test logic, and sampled at a rising edge of the TCK. A TDO (Test Data Out) is a signal for allowing the data from the test logic to be serially outputted, and changes an output value of the data at a falling edge of the TCK. The TCK (Test Clock) supplies clocks to the test logic. The TCK is an input terminal for permitting a serial test data path to be exclusively used independently of a system clock inherent to the component. A TMS (Test Mode Select) is a signal for controlling a test operation, and sampled at the rising edge of the TCK. This signal is decoded by a TAP controller. A TRST (Test Reset) is a negative logic symbol for initializing the TAP controller asynchronously, and is optionally used.
The integrated circuit
210
in which such boundary scan element is integrated can be tested for its operation state and its connection with any external equipment according to the procedures described below.
First, when it is checked whether an internal logic
211
of the integrated circuit
210
is good or bad, serial data (test data) is shifted while the test data is supplied to a TDI terminal
220
of the integrated circuit
210
, and the test data is set in each boundary cell
214
provided for corresponding one of input terminals
212
. In this situation, the integrated circuit
210
is operated, and thereafter the data is allowed to be shifted, which has already been set in each boundary cell
214
provided for corresponding one of output terminals
213
. The shifted data is permitted to be outputted from a TDO terminal
221
, whereby it is checked whether the internal logic
211
of the integrated circuit
210
is good or bad, based on a correlation between serial data obtained (test result data) and the test data inputted to the integrated circuit
210
.
Furthermore, the boundary scan testing method can be executed also for a plurality of integrated circuits as long as the boundary scan element is incorporated in each of the integrated circuits.
For example, as for the plurality of integrated circuits
210
loaded on a board
226
as shown in
FIG. 4
, disconnections of printed patterns between the integrated circuits
210
can be checked, in addition to a test of the integrated circuit
210
itself.
In this case, the boundary scan elements incorporated in the plurality of integrated circuits
210
are connected in series. Specifically, the TDO terminal
221
of the first integrated circuit
210
shown in the left in FIG.
4
and the TDI terminal
220
of the second integrated circuit
210
shown in the right in
FIG. 4
are connected. Moreover, an output terminal
229
of a boundary scan controller board
228
provided in a host computer unit
227
is connected to the TDI terminal
220
of the first integrated circuit
210
, and an input terminal
230
of the boundary scan controller board
228
is connected to the TDO terminal
221
of the second integrated circuit
210
. The test procedures are as follows.
In the case where the disconnection and short circuit of the printed pattern are tested, the test data (serial data) is created using a test data creation tool
231
and the like, and the test data (serial data) is outputted from the output terminal
229
of the boundary scan controller board
228
. The test data (serial data) is shifted while the test data is being inputted to the TDI terminal
220
of the first integrated circuit
210
, thereby setting the test data in each boundary cell
214
provided for corresponding one of the output terminals
213
of the first integrated circuit
210
. In this situation, data stored in each boundary cell
214
is outputted from corresponding one of the output terminals
213
provided in the first integrated circuit
210
as shown in
FIG. 5
, and the data from each output terminal
213
is inputted, via each printed pattern
233
constituting a system bus and the like, to corresponding one of the input terminals
212
of the second integrated circuit
210
. Moreover, the data is taken into each boundary cell
214
provided for corresponding one of the input terminals
212
.
Thereafter, the data stored in each boundary cell
214
of the first and second integrated circuits
210
is shifted, and the data is analyzed with a test result analysis tool
232
and the like while the data is taken into an input terminal
230
of the boundary scan controller board
228
. Thus, the check for the disconnection and short circuit of the printed pattern can be performed within a test range
235
of the printed pattern
233
connecting between the integrated circuits
210
.
Next, in the case where the internal logic
211
of each integrated circuit
210
is examined, the test data is shifted while the test data is being outputted from an output terminal
229
of the boundary scan controller board
228
to the TDI terminal
220
of the first integrated circuit
210
. As shown in
FIG. 7
, the test data is set in each boundary cell
214
provided for corresponding one of the input terminals
212
of the first integrated circuit
210
.
Subsequently, the first integrated circuit
210
is operated, and the data obtained by the operation of the first integrated circuit
210
is taken into each boundary cell
214
provided for corresponding one of the output terminals
213
. Thereafter, the data stored in each boundary cell
214
is shifted
Abraham Esaw
De'cady Albert
Kanesaka & Takeuchi
Koken Co. Ltd.
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