Boundary scan with latching output buffer and weak input buffer

Details Boundary scan with latching output buffer and weak input buffer Boundary scan with latching output buffer and weak input buffer

1999-02-26

2000-04-25

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060556595

ABSTRACT:
An electronic integrated circuit includes a signal path connected between the functional logic thereof and an external output terminal thereof which signal path includes a memory circuit. The memory circuit is coupled to the output terminal and is selectively operable to detect and resolve voltage contention at the output terminal, and is also selectively operable to isolate itself from voltages at the output terminal.

REFERENCES:
patent: 5202625 (1993-04-01), Farwell
patent: 5206545 (1993-04-01), Huang
patent: 5260949 (1993-11-01), Hashizume et al.

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