Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-29
2003-09-09
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06618828
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of testing electronic systems and more particularly to strategies for generating boundary scan test sequences for a system that includes one or more nodes enabled by a common enable latch.
2. History of Related Art
The use of boundary scan testing as disclosed in IEEE Standard 1149.1 “Standard Test Access Port and Boundary-Scan Architecture” to test the various assemblies and components of an electronic system is well known. In addition to enabling the testing of the functionality of a particular integrated circuit, boundary scan testing is useful in testing the interconnections between two or more integrated circuits. See, e.g., Angelotti, Apparatus and Method for Testing Interconnections between Semiconductor Devices, U.S. Pat. No. 5,717,701; Angelotti, Method for Testing Interconnections Between Integrated circuits Using a Dynamically Generated Interconnect Topology Model, U.S. Pat. No. 5,757,820; and Angelotti, Method for Avoiding contention During Boundary Scan Testing, U.S. Pat. No. 5,909,452 (hereinafter referred to as the “'452 patent”); all of which are incorporated by reference herein. In particular, the '452 patent discloses the arranging of boundary scan test sequences to avoid contention on a system net during a state transition. As an example, a sequence of boundary scan tests may produce a transition from a state in which a first node of a net drives the net with a “1” to a state in which a second node drives the net with a “0.” The '452 patent is primarily addressed to reducing or eliminating contention between the two drivers during the transition period. This type of contention is referred to in this disclosure as inter-sequence contention. Referring to
FIG. 1
, a simplified block diagram of an electronic system
100
for use with an electronic test sequence generated according to the prior art is presented. System
100
includes a set of integrated circuit modules or devices
110
,
120
, and
130
that are interconnected via a set of nets
101
,
102
,
103
, and
104
. Each net connects a set of nodes. As examples, Net
1
101
connects nodes
114
a,
134
a,
and
124
c
while Net
2
102
connects nodes
114
b
and
134
b,
and so forth. Each integrated circuit includes a set of boundary scan cells that are suitable for use with a boundary scan test. More specifically, first integrated circuit
110
includes a set of boundary scan cells
111
a,
111
b,
111
c,
112
a,
112
b,
and
112
c.
Boundary scan cells
111
a,
111
b,
and
111
c
are referred to herein as logic scan cells. Each logic scan cell is coupled (via a connection not depicted in
FIG. 1
) to a logic circuit of integrated circuit
110
. Boundary scan cells
112
a,
112
b,
and
112
c
are referred to herein as enable scan cells. Each enable scan cell
112
controls a corresponding driver
113
of integrated circuit
110
. Each driver
113
drives an output signal from a corresponding logic cell
111
onto a corresponding node
114
. Similarly with respect to second integrated circuit
120
, where each node
124
is driven by a corresponding driver
123
, which is enabled by a corresponding enable scan cell
122
, and with respect to third integrated circuit
130
, where each node
134
is driven by a corresponding driver circuit
133
, which is enabled by a corresponding enable scan cell
132
.
It will be appreciated that each scan enable cell
112
,
122
, and
132
includes, at a minimum, a latch circuit that consumes valuable area of the corresponding integrated circuit device. For a variety of reasons including the desire to reduce die size, the use of standardized library packages, and a lack of awareness with respect to how particular designs can affect the testing of the device, scan enable cells
112
are frequently eliminated from a design. More specifically, it is not uncommon to encounter boundary scan implementations in which the driver circuits for multiple scan logic cells are controlled by a common or shared scan enable cell. Utilizing a common enable cell to control multiple driver circuits beneficially reduces the transistor count of the design but, unfortunately, introduces a level of complexity to the process of generating boundary scan test sequences that has not been previously considered. In particular, the presence of nodes that are tied to driver circuits controlled by a common enable circuit can produce a condition in which two or more nodes attempt to simultaneously drive a given net when conventional test sequence generation schemes are employed. The potential damage that contending driver circuits can cause to the reliability and functionality of their corresponding devices makes it highly desirable to devise a method and system that accounts for the possibility of commonly enabled driver circuits.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a boundary scan test sequence generation method and an associated system and computer program product that account for designs in which multiple nodes are enabled by a common enable latch. Broadly, speaking the invention contemplates a method of determining sequences for testing an electronic system that is comprised of a set of nets. Each net of the system provides an interconnect between a set of nodes. The method includes a step in which nodes that are enabled by a common enable latch (referred to herein as commonly enabled nodes) within the system are identified. Each commonly enabled node is associated with a node group. Each node group includes the set of nodes that share a common enable latch. Contending node group pairs within the system are then identified. A contending node group pair is any pair of node groups in which at least one commonly enabled node of the first node group and at least one node of the second node group share a common net. Sequence numbers, preferably for use in defining a boundary scan test sequence, are then assigned to each commonly enabled node in the system. The assignment of the sequence numbers is performed such that sequence numbers for each node within a node group are the same, while sequence numbers associated with pairs of contending node groups differ. In one embodiment, the method further includes the step of assigning sequence numbers to nodes that are controlled by a dedicated (i.e., non-shared) enable latch. The assignment of commonly enabled nodes is preferably prioritized over the assignment of non-shared nodes.
In one embodiment, the steps of identifying contending node group pairs and assigning sequence numbers to each commonly enabled node is achieved with a reiterative process that is repeated for each net in the system and for each node on each net. Initially, a sequence number is assigned to the commonly enabled node. Then it is determined whether the sequence number assigned to the current node results in “intrasequence” contention with a commonly enabled node of a previous net. Intrasequence contention results if the sequence number assigned to the current node matches the sequence number assigned to a previous node and the two nodes belong to contending node group pairs. That is, contention results if at least one node from the node group to which the current node belongs is connected to at least one node from the node group of the previous node via at least one net of the system and the two nodes share a common sequence number. Thus, the term intrasequence contention is used in this disclosure to emphasize a distinction between the type of contention addressed by the present invention and the contention under consideration in the '452 patent discussed in the background section above. If the sequence number assigned to the current node does result in intrasequence contention, a new sequence number that does not generate contention is determined for the current node. When a new sequence number is assigned to a node, the new sequence number is then assigned to all previously considered nodes from the same node g
Chung Phung M.
International Business Machines - Corporation
Lally Joseph P.
McBurney Mark E.
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