Boundary scan tester for logic devices

Details Boundary scan tester for logic devices Boundary scan tester for logic devices

2008-05-27

2008-05-27

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000

Reexamination Certificate

active

07380187

ABSTRACT:
A boundary scan tester is provided for testing logic devices. The boundary scan tester includes a boundary scan register, a data decompressor, a data compressor, and a derived boundary scan register. The boundary scan register registers the applied test vectors and test responses of a logic device, and the data decompressor is coupled to an input of the boundary scan register for decompressing the applied compressed test vectors. The data compressor is coupled to an output of the boundary scan register for compressing the test responses, and the derived boundary scan register is coupled to an input of the decompressor and an output of the compressor for storing and shifting in/out the compressed test vectors and test responses.

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patent: 6556037 (2003-04-01), Shiraishi
patent: 6748456 (2004-06-01), Stanton et al.

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