Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-07-03
2003-08-26
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S726000
Reexamination Certificate
active
06611934
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in a general to integrated circuits, and more particularly to a test cell used in an integrated circuit for providing a boundary scan test structure.
BACKGROUND OF THE INVENTION
Due to advances in the fields of board interconnect technology, surface mount packaging and IC density, board level testability is becoming increasingly complex. The combination of advanced board interconnect technology, such as buried wire interconnects and double-sided boards, along with surface mount packaging creates problems for in-circuit testing of the boards. In-circuit testing, the most common board level testing method, depends upon the ability to physically probe the nodes of a circuit board. As board density (the number of ICs on a board) increases, the process of probing the board using traditional techniques becomes more difficult, due to the lack of physical access.
As the IC density (amount of logic on a chip) increases, the number of test patterns required for proper testing likewise increases. In-circuit testing relies on back-driving techniques to force input conditions to test a particular IC in a circuit. When such test is being applied to one IC on a board, neighboring ICs, whose output buffers are tied to the same nodes, may be damaged. The chance of damaging a neighboring IC increases with the length of time it takes to perform a test, which is directly related to the number of test patterns applied, and therefore, related to the IC density.
Therefore, a need has arisen in the industry to provide a test structure which provides access to particular ICs on a board, and allows testing of particular ICs without risk of damage to neighboring ICs.
SUMMARY OF THE INVENTION
In accordance with the present invention, a boundary scan test system is provided which substantially eliminates the disadvantages and problems associated with prior testing systems.
The boundary scan test system of the present invention comprises a first multiplexer connecting a plurality of inputs to a first memory, responsive to control signals provided by a control bus. The output of the first memory is connected to a second memory. The output of the second memory is connected to an input to a second multiplexer along with one or more other inputs. The second multiplexer is controlled by another control signal on the control bus. The output of the first memory and the output of second memory are connected to the first multiplexer as inputs.
The present invention provides a variety of functions for testing purposes. The test cell is operable to both reserve data inputs and control data outputs to and from the cell. The test cell may operate in two modes: “normal” mode and “testing” mode. In normal mode, the test cell provides a data path through which inputs and outputs may propagate freely through the test cell. While in the normal mode, the test cell can also load and shift test data, remain in an idle state, or toggle test data without disturbing the normal operation of the integrated circuit. Further, while in normal mode, a predetermined test data bit may be inserted into the data stream. Also, the test cell may perform a self-test while in the normal mode to insure correct operation of the test cell.
In the test mode, the test cell inhibits the normal flow of data through the test cell. Normally, the test cells in the integrated circuit will have been prepared to output an initial test pattern. While in the test mode, the test cell may perform Idle, Load, Shift, and Toggle operations.
The present invention provides significant advantages over the prior art. First, the test cell of the present invention may be used to perform internal and external boundary testing simultaneously, in order to reduce overall test time. Second, the test cells are capable of sampling or inserting data at the boundary during normal operation of the host integrated circuit. Third, the test cell is synchronous in operation with a free running test clock. Fourth, the present invention provides a method of toggling an IC's output buffers, independent of the IC's application logic, in order to achieve parametric measures and to facilitate boundary test. Fifth, the test cell provides self-testing capabilities.
REFERENCES:
patent: 3739193 (1973-06-01), Pryor
patent: 3789359 (1974-01-01), Clark, Jr. et al.
patent: 3824678 (1974-07-01), Harris et al.
patent: 3831149 (1974-08-01), Job
patent: 3838264 (1974-09-01), Maker
patent: 3873818 (1975-03-01), Barnard
patent: 3976940 (1976-08-01), Chau et al.
patent: 4023142 (1977-05-01), Woessner
patent: 4066882 (1978-01-01), Esposito
patent: 4086375 (1978-04-01), LaChapelle, Jr. et al.
patent: 4092733 (1978-05-01), Coontz et al.
patent: 4108359 (1978-08-01), Proto
patent: 4146835 (1979-03-01), Chnapko et al.
patent: 4161276 (1979-07-01), Sacher et al.
patent: 4216539 (1980-08-01), Raymond et al.
patent: 4242751 (1980-12-01), Henckels et al.
patent: 4264807 (1981-04-01), Moen et al.
patent: 4286173 (1981-08-01), Oka et al.
patent: 4308616 (1981-12-01), Timoc
patent: 4309767 (1982-01-01), Andow et al.
patent: 4339710 (1982-07-01), Hapke
patent: RE31056 (1982-10-01), Chau et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 4365334 (1982-12-01), Smith et al.
patent: 4366478 (1982-12-01), Masuda et al.
patent: 4390969 (1983-06-01), Hayes
patent: 4426697 (1984-01-01), Petersen et al.
patent: 4439858 (1984-03-01), Petersen
patent: 4483002 (1984-11-01), Groom, Jr. et al.
patent: 4488259 (1984-12-01), Mercy
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 4494066 (1985-01-01), Goel et al.
patent: 4498172 (1985-02-01), Bhavsar
patent: 4503536 (1985-03-01), Panzer
patent: 4504784 (1985-03-01), Goel et al.
patent: 4513373 (1985-04-01), Sheets
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4514845 (1985-04-01), Starr
patent: 4519078 (1985-05-01), Komonytsky
patent: 4553090 (1985-11-01), Hatano et al.
patent: 4575674 (1986-03-01), Bass et al.
patent: 4587609 (1986-05-01), Boudreau et al.
patent: 4594711 (1986-06-01), Thatte
patent: 4597042 (1986-06-01), d'Angeac
patent: 4598401 (1986-07-01), Whelan
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4612499 (1986-09-01), Andresen et al.
patent: 4621363 (1986-11-01), Blum
patent: 4627018 (1986-12-01), Trost et al.
patent: 4628511 (1986-12-01), Stitzlein et al.
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4638313 (1987-01-01), Sherwood et al.
patent: 4646298 (1987-02-01), Laws et al.
patent: 4651088 (1987-03-01), Sawada
patent: 4669061 (1987-05-01), Bhavsar
patent: 4672307 (1987-06-01), Breuer et al.
patent: 4679192 (1987-07-01), Vanbrabant
patent: 4680539 (1987-07-01), Tsai
patent: 4680733 (1987-07-01), Duforestel
patent: 4694293 (1987-09-01), Sugiyama et al.
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4701916 (1987-10-01), Naven et al.
patent: 4701921 (1987-10-01), Powell et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4710933 (1987-12-01), Powell et al.
patent: 4743841 (1988-05-01), Takeuchi
patent: 4745355 (1988-05-01), Eichelberger et al.
patent: 4759019 (1988-07-01), Bentley et al.
patent: 4763066 (1988-08-01), Yeung et al.
patent: 4764926 (1988-08-01), Knight et al.
patent: 4777616 (1988-10-01), Moore et al.
patent: 4783785 (1988-11-01), Hanta
patent: 4791358 (1988-12-01), Sauerwald et al.
patent: 4799004 (1989-01-01), Mori
patent: 4799052 (1989-01-01), Near et al.
patent: 4800418 (1989-01-01), Natsui
patent: 4801870 (1989-01-01), Eichelberger et al.
patent: 4802163 (1989-01-01), Hirabayshi
patent: 4808844 (1989-02-01), Ozaki et al.
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 4812678 (1989-03-01), Abe
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 4821269 (1989-04-01), Jackson et al.
patent: 4825439 (1989-04-01), Sakashita et al.
patent: 4833395 (1989-05-01), Sasaki et al.
patent: 4833676 (1989-05-01), Koo
patent: 4857835 (1989-08-01), Whetsel, Jr.
patent: 4860288 (1989-08-01), Teske et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4864579 (1989-09-01), Kishida et al.
patent: 4866508 (1989-09-01), Eichelberger et a
Bassuk Lawrence J.
Brady W. James
Moise Emmanuel L.
LandOfFree
Boundary scan test cell circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Boundary scan test cell circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Boundary scan test cell circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3112265