Boundary-scan register cell with bypass circuit

Details Boundary-scan register cell with bypass circuit Boundary-scan register cell with bypass circuit

1998-10-21

2001-11-06

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06314539

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to IEEE Standard 1149.1 compliant ICs, and more particularly to Boundary-Scan Register circuits for IEEE Standard 1149.1 compliant PLDs.
BACKGROUND OF THE INVENTION
Programmable Logic Devices (PLDS) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs). The input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBS. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. The CLBs, IOBs and interconnect lines are configured by data stored in a configuration memory of the FPGA.
PLDs have become popular for implementing various logic functions in electronic systems that, in the recent past, were typically implemented by smaller (<100,000 gates) application specific integrated circuits (ASICs). Such functions include glue logic, state machines, data bus logic, digital signal processors and protocol functions. Early PLDs often provided insufficient capacity to implement these functions, so the significant investment of time and money to design, layout and fabricate an ASIC for these functions was justified. However, recent advances in semiconductor and PLD technologies have produced PLDs with the necessary speed and capacity to implement these functions in most applications. Because PLDs are relatively inexpensive and can be programmed in as little as a few hours, the expense associated with the design, layout and fabrication of ASICs became harder to justify. Further, the reprogrammability of many PLDs makes them even more attractive than ASICs because it is possible to update (reconfigure) PLDS, whereas ASICs must be replaced. As such, there is a trend toward the use of PLDs in place of ASICS in electronic systems.
Most electronic systems include multiple ICs (such as PLDS, ASICs, memory devices and processors) mounted on a printed circuit board (PCB). Each PCB includes a pattern of printed metal lines (e.g., copper tracks) formed on a board of insulating material. The ICs are typically soldered to the copper tracks at specific locations on the PCB so that the copper tracks provide signal paths between the ICs that are necessary to form the desired electronic system.
After ICs are soldered to a PCB to form an electronic system, the system is typically tested to verify that all of the ICs are properly mounted (e.g., that the copper tracks provide all required IC-to-IC connections). Early electronic systems were tested using mechanical probes (e.g., bed-of-nails fixtures) that contacted the copper tracks of the PcBs and generated test signals for verifying the interconnections between the ICs. However, steady advances in semiconductor technologies have provided highly integrated ICs mounted in packages that have hundreds of pins arranged at very small pitches. Further, trends toward smaller products have forced manufacturers to pack ICs more densely on PCBs. As a result, conventional PCB testing methods using mechanical probes (e.g., bed-of-nails fixtures) are greatly impeded for several reasons. First, to support these highly integrated ICs, modern PCBs must be formed with copper tracks having ever-narrower widths, thereby making conventional testing difficult because test nails having very small physical dimensions are required. Second, the increase in the number of pins requires an increase in the number of copper tracks per PCB, thereby requiring test equipment that is increasingly more expensive to purchase and operate. Third, the dense packing of ICs on each PCB leaves little room for probe contact. Moreover, recent PCB technologies in which surface mounted IC devices are mounted on both sides of each PCB make mechanical probing practically impossible because of the required simultaneous probe contact on both sides of a PCB.
IEEE Standard 1149.1 (Boundary-Scan) was developed to overcome the limitations of conventional mechanical PCB probe testing. IEEE Standard 1149.1 defines a four pin serial interface that drives a 16-state controller (state machine) formed in each compliant IC device. The four pins control transitions of the state machine and facilitate loading of instructions and data into the compliant IC device to accomplish pre-defined tasks. Originally, IEEE Standard 1149.1 was developed to perform a Boundary-Scan Test wherein the interconnections and IC device placement on PCBs are tested through the connection pins of the PCBs (i.e., without the need for a mechanical probe). Since its establishment, the Boundary-Scan Test has been extended to include device functional tests, self-tests and diagnostic capabilities. More recently, the Boundary-Scan Test has been modified to provide In-System Programming, whereby configuration data is transmitted into the configuration memory of a target PLD after the PLD is mounted onto a PCB.
FIG. 1
shows a simplified electronic system provided for the purpose of explaining the basic concepts of Boundary-Scan Test procedures. The simplified electronic system is formed on a PCB
100
and includes a first PLD
110
and a second PLD
120
.
PCB
100
includes copper traces formed on a board of insulating material that provide signal paths between a PCB connector
101
and PLDs
110
and
120
, and between PLDs
110
and
120
. In addition to the copper traces that transmit normal operation signals (not shown), PCB
100
includes four traces for transmitting Boundary-Scan Test signals. These copper traces include a first trace
102
for transmitting test data-in (TDI) signals, a second trace
103
for transmitting test data-out (TDO) signals, a third trace
104
for transmitting test clock (TCK) signals, and a fourth trace
105
for transmitting test mode select (TMS) signals. Boundary-Scan data (TDI/TDO) signals are typically transmitted serially through each compliant device of a system. That is, TDI signals are transmitted on first trace
102
to first PLD
110
, and pass through first PLD
110
along a line
144
(
1
). TDO signals are transmitted from PLD
110
and received as TDI signals by second PLD
120
along a linking trace
106
, and pass through second PLD
120
along a line
144
(
2
). Finally, TDO signals are transmitted from PLD
120
to PCB connector
101
on second trace
103
. In contrast to the data signals, each compliant device receives the TCK and TMS signals in a parallel manner.
Each PLD of an electronic system includes IOBs that configure the device terminals (pins) for transmitting signals to or from the PLD's programmable core logic circuitry. As shown in
FIG. 1
, first PLD
110
includes I/O terminals
112
that transmit/receive signals via lines
114
through respective IOBs
116
to/from programmable core logic circuit
118
. Similarly, second PLD
120
includes I/O terminals
122
that transmit/receive signals via lines
124
through IOBs
126
to/from core logic circuit
128
.
Unlike ASICs, the functions performed by both core logic circuit
118
and IOBs
116
of PLD
110
are determined by a user after fabrication. That is, the user determines the function or functions to be performed by the programmable interconnect and logic circuitry associated with a PLD. Similarly, the user determines which of the I/O pins will be use

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