Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-08-13
2001-02-27
De Cady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S725000
Reexamination Certificate
active
06195774
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices (ICs), and more particularly to a boundary-scan method for use during in-system programming and test of an IC.
BACKGROUND OF THE INVENTION
Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic functions. There are several types of PLDS, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture, and include a central interconnect matrix to transmit signals between the function blocks. Both the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are controlled by configuration data stored in a configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, and programmable interconnect lines that extend between the rows and columns of CLBs. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. Both the CLBs and interconnect lines are controlled by configuration data stored in a configuration memory of the FPGA.
PLDs are programmed (configured) using data generated by place-and-route software. The PLD programming process typically begins after the user enters his/her logic operation into a computer/workstation in which the place-and-route software is installed. The user then identifies a target PLD architecture and instructs the place-and-route software to generate configuration data which, when entered into the configuration data of the target PLD, programs the target PLD to implement the logic operation. The place-and-route software begins this process by accessing a stored description of the target PLD and the logic operation entered by the user. The place-and-route software then divides the logic operation into inter-related logic portions that can be implemented in the individual function blocks/CLBs of the target PLD, as identified in the PLD description. The place-and-route software then “places” (assigns) the logic portions to specific function blocks/CLBs associated with the target PLD. Routing data is then generated by identifying specific interconnect resources of the target PLD that can be linked to form the necessary signal paths between the inter-related logic portions assigned to the function blocks/CLBs. The placement and routing data is then combined to form configuration data that is converted into a bit map file that, when transmitted into the configuration memory of the target PLD, causes the target PLD to implement the logic function.
PLDs have become popular for implementing various functions in electronic systems that, in the recent past, were typically implemented by smaller (<100,000 gates) application specific integrated circuits (ASICs). Such functions include glue logic, state machines, data bus logic, digital signal processors and protocol devices. Early PLDs often provided insufficient capacity to implement these functions, so the significant investment of time and money to design, layout and fabricate an ASIC for these functions was justified. However, recent advances in semiconductor and PLD technologies have produced PLDs with the necessary speed and capacity to implement these functions in most applications. Because PLDs are relatively inexpensive and can be programmed in as little time as a few seconds, the expense associated with the design, layout and fabrication of ASICs became harder to justify. Further, the reprogrammability of many PLDs makes them even more attractive than ASICs because it is possible to update (reconfigure) PLDs, whereas ASICs must be replaced. As such, there is a trend toward the use of PLDs in place of ASICS in electronic systems.
Most electronic systems include multiple ICs (such as PLDS, ASICs, memory devices and processors) mounted on a printed circuit board (PCB). Each PCB includes a pattern of printed metal lines (e.g., copper tracks) formed on a board of insulating material. The ICs are typically soldered to the copper tracks at specific locations on the PCB so that the copper tracks provide signal paths between the ICs that are necessary to form the desired electronic system.
After ICs are soldered to a PCB to form an electronic system, the system is typically tested to verify that all of the ICs are properly mounted (e.g., that the copper tracks provide all required IC-to-IC connections). Early electronic systems were tested using mechanical probes (e.g., bed-of-nails fixtures) that contacted the copper tracks of the PCBs and generated test signals for verifying the interconnections between the ICs. However, steady advances in semiconductor technologies have provided highly integrated ICs mounted in packages that have hundreds of contact points (e.g., pins) arranged at very small pitches. Further, trends toward smaller products have forced manufacturers to pack ICs more densely on PCBs. As a result, conventional PCB testing methods using mechanical probes (e.g., bed-of-nails fixtures) are greatly impeded for several reasons. First, to support these highly integrated ICs, modern PCBs must be formed with copper tracks having ever-narrower widths, thereby making conventional testing difficult because test nails having very small physical dimensions are required. Second, the increase in the number of device contact points requires an increase in the number of copper tracks per PCB, thereby requiring test equipment that is increasingly more expensive to purchase and operate. Third, the dense packing of ICs on each PCB leaves little room for probe contact. Moreover, recent PCB technologies in which surface mounted IC devices are mounted on both sides of each PCB make mechanical probing practically impossible because of the required simultaneous probe contact on both sides of a PCB.
IEEE Standard 1149.1 (Boundary-Scan) was developed to overcome the limitations of conventional mechanical PCB probe testing. IEEE Standard 1149.1 defines a four pin serial interface that drives a 16-state controller (state machine) formed in each compliant IC device. The four pins control transitions of the state machine and facilitate loading of instructions and data into the compliant IC device to accomplish pre-defined tasks. Originally, IEEE Standard 1149.1 was developed to perform Boundary-Scan Test procedures wherein the interconnections and IC device placement on PCBs are tested through the connection pins of the PCBs (i.e., without the need for a mechanical probe). Since its establishment, some implementations of Boundary-Scan have been extended to include additional test procedures such as device functional tests, self-tests and diagnostics. More recently, Boundary-Scan has been modified to provide In-System Programming, whereby configuration data is transmitted into a target PLD after the PLD is mounted onto a PCB.
FIG. 1
shows a simplified electronic system provided for the purpose of explaining the basic concepts of Boundary-Scan Test procedures. The simplified electronic system is formed on a PCB
100
and includes a first IC
110
and a second IC
120
.
PCB
100
includes copper traces formed on a board of insulating material that provide signal paths between a PCB connector
101
and ICs
110
and
120
, and between ICs
110
and
120
. In addition to the copper traces that transmit normal operation signals (not shown), PCB
100
includes four traces for transmitting Boundary-Scan Test signals. These copper traces include a first trace
102
for transmitting test data-in (TDI) signals, a second trace
103
for transmitting test data-out (TDO) signals, a third trace
104
for transmitting test clock (TCK) signals, and a fourth trace
105
for transmitting test mode select (TMS) signals. Boundary-Scan data (TDI/TDO) signals are typically transmitted serially through each compliant device of a system. That is, TDI signals are tra
Bever Patrick T.
Bever Hoffman & Harms LLP
Cady Albert De
Cartier Lois D.
Lin Samuel
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