Boundary scan method for terminating or modifying integrated cir

Details Boundary scan method for terminating or modifying integrated cir Boundary scan method for terminating or modifying integrated cir

1998-12-03

2000-12-05

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

061580341

ABSTRACT:
A JTAG Boundary Scan method by which the on-chip system logic (OCSL) of an integrated circuit is changed by use of a state machine which, among other functions, allows a predefined set of instructions to be loaded into an Instruction Register and then executed. The predefined instructions are designed to follow in sequence after certain other previous instructions. The instructions change the OCSL from one state to another state and allows the state to be changed without the need of a full device reset. Additional instructions within this invention were created to have attendant operating modes for which termination is self timed within the integrated circuit. Additional instructions further control the implementation of instruction execution within the state machine.

REFERENCES:
patent: 5404358 (1995-04-01), Russell
patent: 5448576 (1995-09-01), Russell
patent: 5459737 (1995-10-01), Andrews
patent: 5495487 (1996-02-01), Whetsel, Jr.
patent: 5528610 (1996-06-01), Edler et al.
IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc., Oct. 21, 1993.

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