Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-09-02
2001-02-27
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06195775
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a boundary design of a chip. More particularly, the present invention relates to a boundary scan latch configuration for generalized scan designs in a single clock chip design.
BACKGROUND OF THE INVENTION
In designing large scale integration (LSI) circuits or very large scale integration (VLSI) circuits, one important step is to incorporate testing circuits for the designs. The principle is to design testing methods concurrently with the architectural considerations of the designs as opposed to be left until fabricated chip or components of the chip have been made. This manufacturing test principle has been well recognized by the LSI and VLSI design industry and is commonly called Design For Test (DFT).
The testing of large scale integration (LSI) packages, very large scale integration (VLSI) packages, and application-specific integrated circuits (ASIC) has become increasingly important as these components and circuits continue to increase in gate densities. One well known testing scheme is called Logic Built-In Self-Test (LBIST). LBIST is accomplished using a LBIST controller which scans data to functional logic units on the chip, cycles system clocks and receives output data from the chip via scanning. The outputted data is compressed and compared with the expected data so as to determine the accuracy of the chip design and the performance thereof. Two other types of tests often referred to as INTEST and RUNBIST are similar to the LBIST. INTEST and RUNBIST are standard tests defined by IEEE 1149.1 Standard (hereinafter referred to “Standard”). They are optional tests that allow testing of an on-chip system logic. Another Standard test is called EXTEST. EXTEST is a mandatory Standard function that allows testing off-chip data paths. There are many similar off-chip tests, one of which is referred to WIRETEST which has a minor modification to the EXTEST to reduce test patterns. A further mandatory Standard function is called SAMPLE/PRELOAD. SAMPLE/PRELOAD allows taking a snapshot of a normal operation of the chip. Lastly, each chip, besides operating in its various test modes and a SAMPLE/PRELOAD mode, operates a function mode, that is a normal customer use mode or a function logic mode in a normal operation. Details of the Standard modes for EXTEST, RUNBIST, INTEST and SAMPLE/PRELOAD can be found in the “IEEE Standard Test Access Port and Boundary-Scan Architecture” (published by IEEE, STD 1149.1-1990, including STD 1149.1A-1993, Oct. 21, 1993, ISDN 1-55937-350-4).
To implement the above various modes, the boundary configuration of a chip, e.g. Inputs or Outputs or Common Inputs/Outputs (CIO), has also to be redesigned to accommodate these and other modes.
In addition, in a chip design, clock designs and clock signal distribution networks continue to evolve as faster chips are required. Accordingly, a single clock distribution with a minimal gating at the ends of the trees (e.g. at the chip boundary) is desired. As a result, a single clock and gates replace the multiple system and scan clocks used in conventional chip designs. However, this single clock requirement complicates the chip design for the boundary configuration, especially when the boundary configuration adapts for boundary scan latch configuration with GSD as there is a need for supporting a Standard Clock (or TCK). The TCK clock generally performs on the Standard's Test Access Port (TAP). For a boundary scan, the functions include: scanning data in and out of the Boundary Scan Scan Chain, Sampling Data into the Boundary Scan latches, and driving data from the Boundary Scan latches in selected modes.
Another problem is that there are limited Inputs/Outputs (I/O) in a chip. The limited I/O count further requires a creative boundary configuration that allows sharing functional I/O with test I/O pins.
Therefore, there is a need to design a scannable boundary configuration in a single clock environment for different function and test modes. There is also a need to design a scannable boundary configuration for Generalized Scan Designs. There is further a need to design a scannable boundary configuration which shares its I/Os with test-only I/O pins. The present invention provides a solution to the above and other problems and offers advantages over conventional boundary designs.
SUMMARY OF THE INVENTION
The present invention relates generally to a boundary design of a chip. More particularly, the present invention relates to a boundary scan latch configuration for generalized scan designs in a single clock chip design.
In one embodiment of the present invention, a boundary circuit includes: at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell.
Still in one embodiment, the internal latch includes a pair of shift register latches controlled by the boundary scan clock input, and a scan/hold control signal.
Further in one embodiment of the present invention, an inverter is connected between the input/output cell and the latch.
Yet in one embodiment of the present invention, the at least one control line controls a function mode. During a function mode, a signal is sent to/from at least one internal logic unit of the chip for a normal functional operation.
Still in one embodiment of the present invention, the at least one control line controls an INTEST/RUNBIST mode. During an INTEST/RUNBIST mode, a signal is scanned via the internal latch and sent to at least one internal logic unit of the chip for a test operation.
Additionally in one embodiment of the present invention, the at least one control line controls a LBIST mode. During a LBIST mode, a signal is scanned in via the internal latch and sent to at least one internal logic unit of the chip for a test operation. Also, during the LBIST mode, a signal from at least one internal logic unit of the chip can also be scanned out via the internal latch for analysis.
Further in one embodiment of the present invention, the at least one control line controls an EXTEST/WIRETEST mode. During an EXTEST/WIRETEST mode, a signal is scanned into the internal latch and sent to at least one external logic unit for a test operation. Also, during an EXTEST/WIRETEST mode, a signal from at least one external logic unit can be received by a receiver of the input/output cell and scanned out via the internal latch for analysis.
Yet in one embodiment of the present invention, the at least one control line controls a SAMPLE/PRELOAD mode. During a SAMPLE/PRELOAD mode, the at least one control line is driven into at least one logic unit of the chip so as to take a snapshot of a normal functional operation of the chip.
Additionally in one embodiment of the present invention, the signal can be a data signal or a control signal.
Still in one embodiment of the present invention, the at least one control line controls a driver of the input/output cell.
Further in one embodiment of the present invention, the at least one control line controls a receiver of the input/output cell.
Yet in one embodiment of the present invention, a logic unit is connected to the at least one control line such that a driver of the input/output cell is inhibitable in a test function input sharing operation. An output of a receiver of the input/output cell is shared with a test function input of the chip when the driver is inhibited.
Additional in one embodiment of the present invention, a logic unit is connected to the at least one control line such that a driver is not inhibitable in a test function output sharing operation. An input of the driver is shared with a test function output of the chip when the driver is not inhibited.
Still in one embodiment of the present invention, the boundary scan clock includes a system clock of the chip and a standard clock TCK.
In a second embodiment of the present invention, the boundary scan clock includes a standard clock TCK.
Furth
Douskey Steven Michael
Ganfield Paul Allen
Young Daniel Guy
Cady Albert De
Chase Shelly A
Hollingsworth Mark A.
International Business Machines - Corporation
Xu Min
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