Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-23
2003-12-02
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06658614
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a boundary scan element for use in a boundary scan test method and a communication system in which the element is applied to and used as a communication element, and more particularly to a boundary scan element that enables high-speed transfer of data and a communication system using the element.
BACKGROUND OF THE INVENTION
A boundary scan test method has been proposed as one of the inspection methods by which it is tested, with a plurality of IC chips being disposed on a printed wire board with printed wires formed thereon, whether or not the respective IC chips are connected to the respective printed wires correctly and whether or not there is any break in the respective printed wires, etc.
This boundary scan test method can be applied to integrated circuits (IC chips) into which boundary scan elements are incorporated. For example, as shown in
FIG. 5
, the boundary scan element comprises a plurality of boundary cells
214
disposed individually between input/output terminals of an internal logic circuit
211
for implementing the inherent functions of an integrated circuit
210
, and input/output terminals
212
/
213
of the integrated circuit
210
, a TAP controller (TAP circuit)
219
for controlling input and output of data to the boundary cells
214
, a TDI terminal
220
for receiving test data, a TDO terminal
221
for transmitting test data, a TCK terminal
222
to which a clock signal is input, and a TMS terminal
223
for receiving a mode signal for switching the operation mode of the TAP controller
219
. In addition, as required, the boundary scan element is provided with a bypass register
215
, and an ID CODE register
216
, an instruction register
217
, or a TRS terminal
224
for receiving a reset signal. Incidentally, the bypass register
215
—the instruction register
217
are designated as a boundary scan register (
218
).
Explaining the respective terminals and the signals to be input and output at the respective terminals in detail, TDI (Test Data In) is a signal for serial input of commands or data to a test logic, being sampled on the rising edge of TCK. TDO (Test Data Out) is a signal for serial output of data from the test logic, and an output value is changed on the falling edge of TCK. TCK (Test Clock) supplies a clock to the test logic, and is a dedicated input that allows a serial test data path to be used independent of the system clock inherent to the component. TMS (Test Mode Select) is a signal for controlling test operations, being sampled on the rising edge of TCK. The TAP controller decodes this signal. TRST (Test Reset) is a negative logic symbol for initializing the TAP controller in an asynchronous manner and is optional.
The integrated circuit
210
into which such boundary scan elements are incorporated can be tested on the operation conditions thereof and the connections between the integrated circuit
210
and external devices thereof in accordance with the procedures to be mentioned below.
First, to check for a quality of the internal logic
211
of the integrated circuit
210
, serial data (test data) is shifted and set to the respective boundary cells
214
corresponding to the respective input terminals
212
while being input to the TDI terminal
220
of the integrated circuit
210
. After the integrated circuit
210
is activated under this condition, the data having been set to the respective boundary cells
214
corresponding to the respective output terminals
213
is shifted to be output from the TDO terminal
221
. In accordance with the relationship between the resultant serial data (test result data) and the test data input to the integrated circuit
210
, it is tested whether or. not the internal logic
211
of the integrated circuit
210
is good.
Furthermore, the boundary scan test method can be applied to a plurality of integrated circuits if boundary scan elements are incorporated therein.
For example, for a plurality of integrated circuits
210
mounted on the board
226
as shown in
FIG. 6
, the integrated circuits
210
can be tested on themselves in conjunction with a test on a break in printed patterns between the integrated circuits
210
.
In this case, the respective boundary scan elements incorporated into the plurality of integrated circuits
210
are connected in series. Specifically, the TDO terminal
221
of a first integrated circuit
210
(on the left in the figure) is connected to the TDI terminal
220
of a second integrated circuit
210
(on the right in the figure). Furthermore, the output terminal
229
of the boundary scan controller board
228
provided in the host computer unit
227
or the like is connected to the TDI terminal
220
of the first integrated circuit
210
. Still furthermore, the input terminal
230
of the boundary scan controller board
228
is connected to the TDO terminal
221
of the second integrated circuit
210
. The test procedure is as follows.
In the case of testing a break, short-circuit, or the like in printed patterns, test data (serial data) is prepared using a test data preparing tool
231
or the like, and then output from the output terminal
229
of the boundary scan controller board
228
. Then, while being input to the TDI terminal
220
of the first integrated circuit
210
, the data is shifted and set to the respective boundary cells
214
corresponding to the respective output terminals
213
of the integrated circuit
210
. Under this condition, the data stored in these respective boundary cells
214
is output from the respective output terminals
213
provided on the first integrated circuit
210
as shown in FIG.
7
. Additionally, the data is input to the respective input terminals
212
of the second integrated circuit
210
via respective printed patterns
233
constituting a system bus or the like, and furthermore captured by the respective boundary cells
214
corresponding to these respective input terminals
212
.
Thereafter, the data stored in the respective boundary cells
214
of these respective integrated circuits
210
is shifted, and analyzed using the test result analysis tool
232
while being captured by the input terminal
230
of the boundary scan controller board
228
. This allows a test on the break, short-circuit and the like within the test range
235
of the printed pattern
233
that connects between the integrated circuits
210
.
Now, in the case of testing the internal logic
211
of the respective integrated circuits
210
, test data is output from the output terminal
229
of the boundary scan controller board
228
. Then, while being input to the TDI terminal
220
of the first integrated circuit
210
, the data is shifted and set to the respective boundary cells
214
corresponding to the respective input terminals
212
of the integrated circuit
210
as shown in FIG.
8
.
Subsequently, the integrated circuit
210
is activated and the respective boundary cells
214
corresponding to the respective output terminals
213
are allowed to capture the resultant data. Thereafter, the data stored in these respective boundary cells
214
is shifted and output from the TDO terminal
221
of the first integrated circuit
210
. At this time, the boundary scan controller board
228
drives the second integrated circuit
210
into a bypass state as shown in FIG.
7
. This allows the data output from the TDO terminal
221
to bypass the second integrated circuit
210
and to be captured by the input terminal
230
of the boundary scan controller board
228
. Additionally, the test analysis tool
232
or the like is used to analyze the captured data, thereby allowing a test on whether or not the first integrated circuit
210
operates properly.
Now, in the case of testing the second integrated circuit
210
, in a like manner, the boundary scan controller board
228
drives the first integrated circuit
210
into a bypass state as shown in FIG.
8
. Thereafter, test data is output from the output terminal
229
of the boundary scan controller board
228
and is allowed to bypass th
Abraham Esaw
De'cady Albert
Kanesaka & Takeuchi
Koken Co. Ltd.
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